公开(公告)号：US20160079208A1

公开(公告)日：2016-03-17

申请号：US14821767

申请日：2015-08-09

Applicant: Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

Inventor： Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8113 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/17136 ,  H01L2224/17179

Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

Abstract translation: 一个实施例包括半导体封装，包括：衬底; 安装在所述基板上的第一半导体芯片; 安装在所述第一半导体芯片的顶表面上的第二半导体芯片; 设置在所述第一和第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片的连接凸块; 以及第一散热部，其设置在第一和第二半导体芯片之间的第一半导体芯片的顶表面上并且与第二半导体芯片的底表面间隔开。