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    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
    具有电极的半导体器件及其制造方法

    公开(公告)号：US20150123284A1

    公开(公告)日：2015-05-07

    申请号：US14470366

    申请日：2014-08-27

    Applicant: Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

    Inventor： Chajea JO ,  Taeje CHO ,  Hyunsoo CHUNG

    IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768

    CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

    Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
    半导体封装及其制造方法

    公开(公告)号：US20160013174A1

    公开(公告)日：2016-01-14

    申请号：US14736247

    申请日：2015-06-10

    Applicant: Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

    Inventor： Sang-Uk HAN ,  Seungwon PARK ,  Un-Byoung KANG ,  Taeje CHO

    IPC: H01L25/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

    CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/82 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

    Abstract translation: 本发明构思的实施例提供一种半导体封装及其制造方法。 该方法包括形成沟槽以将第一半导体芯片彼此分开。 形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具 层在基本上垂直于半导体衬底的底表面的方向上。 通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。

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