公开(公告)号：US20160079208A1

公开(公告)日：2016-03-17

申请号：US14821767

申请日：2015-08-09

Applicant: Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

Inventor： Junyeong HEO ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8113 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/17136 ,  H01L2224/17179

Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

Abstract translation: 一个实施例包括半导体封装，包括：衬底; 安装在所述基板上的第一半导体芯片; 安装在所述第一半导体芯片的顶表面上的第二半导体芯片; 设置在所述第一和第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片的连接凸块; 以及第一散热部，其设置在第一和第二半导体芯片之间的第一半导体芯片的顶表面上并且与第二半导体芯片的底表面间隔开。

公开(公告)号：US20170170154A1

公开(公告)日：2017-06-15

申请号：US15357741

申请日：2016-11-21

Applicant: SEUNG-KWAN RYU ,  YONGHWAN KWON ,  YUN SEOK CHOI ,  CHAJEA JO ,  TAEJE CHO

Inventor： SEUNG-KWAN RYU ,  YONGHWAN KWON ,  YUN SEOK CHOI ,  CHAJEA JO ,  TAEJE CHO

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L24/19 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2225/1088

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US20150171028A1

公开(公告)日：2015-06-18

申请号：US14492556

申请日：2014-09-22

Applicant: CHAJEA JO ,  Taeje CHO ,  YUNHYEOK IM

Inventor： CHAJEA JO ,  Taeje CHO ,  YUNHYEOK IM

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package is provided. At least one semiconductor chip is mounted on a package substrate. A mold layer covers the at least one semiconductor chip. The mold layer exposes a portion of a top surface of an uppermost semiconductor chip of the at least one semiconductor chip.

Abstract translation: 提供半导体封装。 至少一个半导体芯片安装在封装衬底上。 模具层覆盖至少一个半导体芯片。 模层暴露至少一个半导体芯片的最上半导体芯片的顶表面的一部分。

公开(公告)号：US20160133613A1

公开(公告)日：2016-05-12

申请号：US14841736

申请日：2015-09-01

Applicant: SUNKYOUNG SEO ,  CHAJEA JO ,  JI HWANG KIM ,  Taeje CHO

Inventor： SUNKYOUNG SEO ,  CHAJEA JO ,  JI HWANG KIM ,  Taeje CHO

IPC: H01L25/10 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/14519 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip.

Abstract translation: 提供半导体封装。 半导体封装包括下半导体封装，其包括下封装衬底和安装在其上的下半导体芯片，以及设置在下半导体封装上的上半导体封装，以包括安装在其上的上封装衬底和上半导体芯片。 上封装衬底包括上部散热图案，下半导体芯片包括通过下半导体芯片连接到上部散热图案的第一通孔，并且第一通孔可以提供用于耗散在下半导体中产生的热的路径 芯片。

公开(公告)号：US20150380394A1

公开(公告)日：2015-12-31

申请号：US14744031

申请日：2015-06-19

Applicant: Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

Inventor： Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.

Abstract translation: 半导体封装可以包括第一半导体芯片，其包括面向封装基板的第一表面，与第一表面相对的第二表面，以及穿透第一半导体芯片的至少一个贯通电极，模制第一半导体芯片的模制层和暴露 第一半导体芯片的第二表面，堆叠在第一半导体芯片的第二表面上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的非导电膜。 第二半导体芯片包括延伸穿过第一半导体芯片的边缘的突出部分。 例如，第二半导体芯片的尺寸可以大于第一半导体芯片的尺寸，因此第二半导体芯片具有突出端。 第二半导体芯片包括电连接到至少一个通孔的至少一个互连端子。