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公开(公告)号：US20170069840A1
公开(公告)日：2017-03-09
申请号：US15049248
申请日：2016-02-22
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： According to one embodiment, a semiconductor memory device includes first-third conductive layers, a semiconductor layer, a resistance change layer and a metal-containing layer. The second conductive layer is separated from the first conductive layer in a first direction. The semiconductor layer is provided between the first and the second conductive layers. The third conductive layer is arranged with the first semiconductor layer in a direction crossing the first direction. The first resistance change layer is provided between the first semiconductor layer and the first conductive layer. The first metal-containing layer is provided between the first resistance change layer and the first conductive layer. The first conductive layer extends in a second direction crossing the first direction. The second conductive layer extends in a third direction crossing the first direction and crossing the second direction. The third conductive layer extends in a direction crossing the first direction.
摘要翻译： 根据一个实施例，半导体存储器件包括第一至第三导电层，半导体层，电阻变化层和含金属层。 第二导电层在第一方向与第一导电层分离。 半导体层设置在第一和第二导电层之间。 第三导电层与第一半导体层沿与第一方向交叉的方向布置。 第一电阻变化层设置在第一半导体层和第一导电层之间。 第一含金属层设置在第一电阻变化层和第一导电层之间。 第一导电层沿与第一方向交叉的第二方向延伸。 第二导电层在与第一方向交叉的第三方向上延伸并与第二方向交叉。 第三导电层沿与第一方向交叉的方向延伸。
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公开(公告)号：US20160293583A1
公开(公告)日：2016-10-06
申请号：US15082546
申请日：2016-03-28
发明人： Chika TANAKA , Keiji IKEDA , Masumi SAITOH
IPC分类号： H01L25/065 , H01L29/78 , H01L27/088
CPC分类号： H01L25/0657 , H01L27/0688 , H01L27/092 , H01L27/1203 , H01L29/7855
摘要： A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.
摘要翻译： 根据实施例的半导体集成电路包括：包括n沟道晶体管和p沟道晶体管的CMOS反相器，n沟道晶体管和p沟道晶体管中的一个设置在n沟道晶体管的另一个之上 和p沟道晶体管。
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3.发明申请SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME 审中-公开半导体存储器件，半导体器件及其制造方法公开(公告)号：US20160268339A1
公开(公告)日：2016-09-15
申请号：US15062672
申请日：2016-03-07
发明人： Kiwamu SAKUMA , Shosuke FUJII , Masumi SAITOH , Toshiyuki SASAKI
CPC分类号： H01L27/249 , H01L27/2454 , H01L29/66666 , H01L45/085 , H01L45/1226 , H01L45/145 , H01L45/146
摘要： According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
摘要翻译： 根据一个实施例，半导体存储器件包括多个第一布线，第二布线，多个存储单元，选择栅极晶体管和第三布线。 第一布线沿着基板的表面沿着第一方向设置，并且在与基板的表面相交的第二方向上。 选择栅极晶体管连接到第二布线的相应的一端。 第三布线共同连接到选择栅晶体管的一端。 选择栅极晶体管包括层叠在第三布线上的第一至第三半导体层和栅电极。 栅电极沿第一方向与第二半导体层相对。 第二半导体层在第一方向上的长度小于第一方向上的第一半导体层和第三半导体层的长度。
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公开(公告)号：US20150262671A1
公开(公告)日：2015-09-17
申请号：US14471492
申请日：2014-08-28
CPC分类号： G06F13/4022 , G11C5/025 , G11C8/12 , G11C16/08 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/144 , H01L45/145 , H01L45/146
摘要： A nonvolatile memory device according to an embodiment includes: a semiconductor substrate; a memory cell array unit provided on an upper side of the semiconductor substrate; an integrated circuit unit provided between the memory cell array unit and the semiconductor substrate; and a peripheral circuit unit provided on the semiconductor substrate. The integrated circuit unit includes: a first contact electrode electrically connected to one of plurality of first interconnection layers; a second contact electrode connected to the peripheral circuit unit; and a first switching element connected between the first contact electrode and the second contact electrode, and conduction between the first contact electrode and the second contact electrode being controlled by a control circuit unit provided in the peripheral circuit unit.
摘要翻译： 根据实施例的非易失性存储器件包括：半导体衬底; 设置在所述半导体衬底的上侧的存储单元阵列单元; 设置在所述存储单元阵列单元和所述半导体基板之间的集成电路单元; 以及设置在半导体衬底上的外围电路单元。 集成电路单元包括：电连接到多个第一互连层之一的第一接触电极; 连接到所述外围电路单元的第二接触电极; 以及连接在第一接触电极和第二接触电极之间的第一开关元件，并且第一接触电极和第二接触电极之间的导通由设置在外围电路单元中的控制电路单元控制。
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公开(公告)号：US20150213887A1
公开(公告)日：2015-07-30
申请号：US14491402
申请日：2014-09-19
发明人： Kensuke OTA , Masumi SAITOH , Kiwamu SAKUMA , Daisuke MATSUSHITA , Yoshihisa IWATA , Chika TANAKA
IPC分类号： G11C13/00 , H01L27/24 , H01L29/786 , H01L45/00
CPC分类号： G11C13/0026 , G11C13/0007 , G11C2213/33 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L29/7869 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/145 , H01L45/146
摘要： A semiconductor memory device comprises: first lines; second lines; memory cells; a first and second select gate transistor; and a control circuit. The first lines are arranged with a certain pitch in a first direction perpendicular to a substrate and are extending in a second direction parallel to the substrate. The second lines are arranged with a certain pitch in the second direction, are extending in the first direction, and intersect the plurality of first lines. The memory cells are disposed at intersections of the first lines and the second lines. The first and second select gate transistors each include a first or second channel line that are connected to a lower end or an upper end of the second line and a first or second gate line. The control circuit controls the first and second select gate transistors independently.
摘要翻译： 半导体存储器件包括：第一线; 第二行 记忆细胞; 第一和第二选择栅晶体管; 和控制电路。 第一线在垂直于衬底的第一方向上以一定间距排列，并且沿平行于衬底的第二方向延伸。 第二线在第二方向上以一定间距排列，沿第一方向延伸，并与多条第一线相交。 存储单元设置在第一行和第二行的交点处。 第一和第二选择栅晶体管各自包括连接到第二线的下端或上端的第一或第二沟道线以及第一或第二栅极线。 控制电路独立地控制第一和第二选择栅极晶体管。
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公开(公告)号：US20170040380A1
公开(公告)日：2017-02-09
申请号：US15227053
申请日：2016-08-03
CPC分类号： H01L27/249 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/145
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.
摘要翻译： 根据一个实施例，存储器件包括第一电极，第二电极，第一层和第二层。 第一电极包括第一元件。 第一层设置在第一电极和第二电极之间。 第一层包括绝缘体或第一半导体中的至少一个。 第二层设置在第一层和第二电极之间。 第二层包括第一区域和第二区域。 第二区域设置在第一区域和第二电极之间。 第二区域包括第二元件。 第二元件的标准电极电位低于第一元件的标准电极电位。 第一区域中的氮浓度高于第二区域中的氮浓度。
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公开(公告)号：US20170033118A1
公开(公告)日：2017-02-02
申请号：US15134969
申请日：2016-04-21
发明人： Shosuke FUJII , Kiwamu SAKUMA , Masumi SAITOH
IPC分类号： H01L27/115 , H01L29/78 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/3065 , H01L21/308 , H01L29/788 , H01L21/3105
CPC分类号： H01L21/02238 , H01L21/02164 , H01L21/02255 , H01L21/02271 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L21/31055 , H01L21/31116 , H01L21/31144 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11578 , H01L29/7843
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括具有第一绝缘层，半导体层和第二绝缘层的第一结构，第一绝缘层和第二绝缘层沿第一方向依次堆叠，第一结构沿第二方向延伸，提供存储单元 在所述半导体层的面向第三方向的表面上并沿第二方向串联连接的第三绝缘层和与所述第一结构的第一和第二端部中的至少一个沿第二方向接触的第三绝缘层，至少不覆盖 第一和第二端部之间的区域的一部分。 半导体层中第二方向的半导体原子的晶格间距大于第一方向上的半导体层中的半导体原子的晶格间距。
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公开(公告)号：US20160276410A1
公开(公告)日：2016-09-22
申请号：US15069540
申请日：2016-03-14
发明人： Harumi SEKI , Takayuki ISHIKAWA , Masumi SAITOH
CPC分类号： H01L27/2463 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L45/165 , H01L45/1675
摘要： According to one embodiment, a memory device includes a first layer, a second layers, a third layer provided between the first layer and the second layer, and first electrodes. The first layer includes first interconnections and a first insulating portion provided between the first interconnections. The second layer includes second interconnections and a second insulating portion provided between the second interconnections. The third layer includes first and second portions including silicon oxide. The first portion is provided between the first and the second interconnections. The second portion is provided between the first and the second insulating portions. The first electrodes are provided between the first interconnections and the first portion, and include a first material. The second interconnections include a second material. The first material is easier to ionize than the second material. A density of the first portion is lower than a density of the second portion.
摘要翻译： 根据一个实施例，存储器件包括第一层，第二层，设置在第一层和第二层之间的第三层以及第一电极。 第一层包括第一互连和设置在第一互连之间的第一绝缘部分。 第二层包括第二互连和设置在第二互连之间的第二绝缘部分。 第三层包括包括氧化硅的第一和第二部分。 第一部分设置在第一和第二互连之间。 第二部分设置在第一和第二绝缘部分之间。 第一电极设置在第一互连和第一部分之间，并且包括第一材料。 第二互连包括第二材料。 第一种材料比第二种材料更容易离子化。 第一部分的密度低于第二部分的密度。
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公开(公告)号：US20150076439A1
公开(公告)日：2015-03-19
申请号：US14446419
申请日：2014-07-30
发明人： Masumi SAITOH , Takayuki ISHIKAWA , Shosuke FUJII , Hidenori MIYAGAWA , Chika TANAKA , Ichiro MIZUSHIMA
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L27/2436 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1616 , H01L45/1641
摘要： According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.
摘要翻译： 根据一个实施例，存储器件包括第一电极，第二电极和可变电阻层。 第二电极包括金属。 金属比第一电极的材料更容易电离。 可变电阻层设置在第一电极和第二电极之间。 可变电阻层包括第一层和第二层。 第一层具有较高的结晶速率。 第二层接触第一层。 第二层具有相对低的结晶速率。 第一层和第二层沿着连接第一电极和第二电极的方向堆叠。
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公开(公告)号：US20140131811A1
公开(公告)日：2014-05-15
申请号：US14072948
申请日：2013-11-06
发明人： Masumi SAITOH , Kensuke OTA , Toshinori NUMATA , Chika TANAKA , Shinichi YASUDA , Kosuke TATSUMURA , Koichiro ZAITSU
CPC分类号： H01L27/1211 , H01L21/845 , H01L27/1104
摘要： A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature.
摘要翻译： 实施例的半导体器件包括：第一晶体管，具有布置在第一突出半导体区域中的第一源极区域和第一漏极区域，第一沟道区域在其上部中的与第一方向垂直的截面中具有第一角部 所述第一角部具有第一曲率半径; 第二晶体管，具有布置在第二突出半导体区域中的第二源极区域和第二漏极区域;以及第二沟道区域，所述第二沟道区域在其上部具有与第二方向垂直的截面中的第二角部， 具有大于第一曲率半径的第二曲率半径。
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