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    INTEGRATED CIRCUIT
    1.
    发明申请
    INTEGRATED CIRCUIT 有权
    集成电路

    公开(公告)号：US20170033122A1

    公开(公告)日：2017-02-02

    申请号：US15220772

    申请日：2016-07-27

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Koichiro ZAITSU

    IPC: H01L27/118 ,  H01L23/528

    CPC classification number: G11C13/0002 ,  G11C17/165 ,  G11C17/18 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H03K19/1736 ,  H03K19/17744

    Abstract: An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.

    Abstract translation: 根据实施例的集成电路包括：包括至少三个第一布线的第一布线线组; 包括第二布线的第二布线组; 每个包括第一和第二端子的第一电阻变化元件和第一电阻变化层; 第一选择电路，包括连接到第二布线的第一输入端和第一输出端，​​第一选择电路从第一输入端选择第一输入端，并从第一输出端输出信息; 第三和第四布线; 以及第二选择电路，从所述第一布线组选择两条第一布线，将所选择的两个第一布线中的一条连接到所述第三布线，并将所选择的两条第一布线中的另一布线连接到所述第四布线。

    RECONFIGURABLE CIRCUIT
    2.
    发明申请
    RECONFIGURABLE CIRCUIT 有权
    可重新连接电路

    公开(公告)号：US20160276025A1

    公开(公告)日：2016-09-22

    申请号：US15056083

    申请日：2016-02-29

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Kosuke TATSUMURA ,  Koichiro ZAITSU

    IPC: G11C13/00

    CPC classification number: G11C13/0028 ,  G11C13/0023 ,  G11C29/785 ,  G11C29/808 ,  G11C2213/77

    Abstract: According to one embodiment, a reconfigurable circuit includes circuit blocks arranged with a matrix of A rows and B columns. Each of the circuit blocks includes M row conductive lines, N column conductive lines crossing the row conductive lines, output inverters each having input and output terminals, the input terminal of each output inverter connected to corresponding one of the row conductive lines, input inverters each having input and output terminals, the output terminal of each input inverter connected to corresponding one of the column conductive lines, and resistance change elements between the row conductive lines and the column conductive lines, each of the resistance change elements including a first terminal and a second terminal, the first terminal being connected to corresponding one of the row conductive lines, the second terminal being connected to corresponding one of the column conductive lines.

    Abstract translation: 根据一个实施例，可重构电路包括以A行和B列的矩阵排列的电路块。 每个电路块包括M行导线，与行导线交叉的N列导线，每个具有输入和输出端的输出反相器，每个输出反相器的输入端连接到相应的行导线，每个输入反相器 具有输入和输出端子，每个输入反相器的输出端子连接到相应的列导线之一，以及在行导线和列导线之间的电阻变化元件，每个电阻变化元件包括第一端子和 所述第一端子连接到所述行导线中的相应一个，所述第二端子连接到所述列导电线中的对应的一个。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20160078935A1

    公开(公告)日：2016-03-17

    申请号：US14854361

    申请日：2015-09-15

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Koichiro ZAITSU

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/74 ,  G11C2213/79

    Abstract: A semiconductor integrated circuit includes: first and second wiring lines; resistive change memories disposed intersection regions of the first and second wiring lines; and a control circuit controlling the first and second drivers to select one of the first wiring lines and one of the second wiring lines, the control circuit changing a resistance of the selected one of the resistive change memories from the first resistive state to the third resistive state, and then changing the resistive state of the selected one of the resistive change memories from the third resistive state to the second resistive state.

    Abstract translation: 一种半导体集成电路包括：第一和第二布线; 电阻变化存储器设置第一和第二布线的相交区域; 以及控制电路，其控制所述第一和第二驱动器以选择所述第一布线和所述第二布线中的一个，所述控制电路将所述电阻变化存储器中的所述一个电阻变化存储器的电阻从所述第一电阻状态改变为所述第三电阻 状态，然后将所选择的一个电阻变化存储器的电阻状态从第三电阻状态改变到第二电阻状态。

    PROGRAMMABLE LOGIC SWITCH
    5.
    发明申请
    PROGRAMMABLE LOGIC SWITCH 有权
    可编程逻辑开关

    公开(公告)号：US20130248959A1

    公开(公告)日：2013-09-26

    申请号：US13772484

    申请日：2013-02-21

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Mari MATSUMOTO ,  Shinichi YASUDA ,  Masato ODA ,  Kosuke TATSUMURA ,  Koichiro ZAITSU ,  Shuou NOMURA ,  Yoshihisa IWATA

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L27/0688

    Abstract: According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line.

    Abstract translation: 根据一个实施例，可编程逻辑开关包括在第一路径晶体管之上的第一和第二字线，通过第一和第二字线并连接到第一路径晶体管的第一柱，穿过第一和第二字的第二柱 并且连接到第一路径晶体管，第一柱和第一字线之间的第一存储器件，第一柱和第二字线之间的第二存储器件，第二柱和第一字线之间的第三存储器件 以及在第二柱和第二字线之间的第四存储器件。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    7.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20160078933A1

    公开(公告)日：2016-03-17

    申请号：US14849047

    申请日：2015-09-09

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Haiyang PENG ,  Koichiro ZAITSU ,  Shinichi YASUDA

    IPC: G11C13/00

    CPC classification number: G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C17/165 ,  G11C17/18 ,  G11C29/787 ,  G11C2213/15 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79

    Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode.

    Abstract translation: 根据一个实施例，半导体集成电路包括包括第一和第二电极以及它们之间的电阻变化膜的存储单元，以及控制第一和第二电极之间的电位差的控制电路。 控制电路通过向第一电极施加第一电位并且通过将小于第一电位的第二电位施加到第二电极来将存储器单元可逆地改变为第一电阻状态。 控制电路通过向第一电极施加第三电位并且通过向第二电极施加小于第三电位的第四电位，将存储器单元可逆地改变为第二电阻状态。

    PROGRAMMABLE LOGIC DEVICE
    8.
    发明申请
    PROGRAMMABLE LOGIC DEVICE 有权
    可编程逻辑器件

    公开(公告)号：US20150263072A1

    公开(公告)日：2015-09-17

    申请号：US14610305

    申请日：2015-01-30

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Koichiro ZAITSU ,  Shinichi YASUDA

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0071 ,  H01L45/04 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

    Abstract: A programmable logic device includes: a first memory element including a first electrode connected to a first wiring line, a second electrode, and a first resistive change layer, a resistance between the first and second electrodes being changed from a low-resistance state to a high-resistance state by applying, to the second electrode, a voltage higher than a voltage applied to the first electrode; a second memory element. including a third electrode connected to the second electrode, a fourth electrode connected to a second wiring line, and a second resistive change layer, a resistance between the third and fourth electrodes being changed from a low-resistance state to a high-resistance state by applying, to the fourth electrode, a voltage higher than a voltage applied to the third electrode; and a first transistor, of which a gate is connected to the second electrode and the third electrode.

    Abstract translation: 可编程逻辑器件包括：第一存储元件，包括连接到第一布线，第二电极和第一电阻变化层的第一电极，第一和第二电极之间的电阻从低电阻状态改变为 向第二电极施加高于施加到第一电极的电压的电压的高电阻状态; 第二存储元件。 包括连接到第二电极的第三电极，连接到第二布线的第四电极和第二电阻变化层，第三和第四电极之间的电阻由低电阻状态改变为高电阻状态，由 向所述第四电极施加高于施加到所述第三电极的电压的电压; 以及第一晶体管，其栅极连接到第二电极和第三电极。

    Nonvolatile Programmable Logic Switch
    9.
    发明申请
    Nonvolatile Programmable Logic Switch 有权
    非易失性可编程逻辑开关

    公开(公告)号：US20150244373A1

    公开(公告)日：2015-08-27

    申请号：US14624961

    申请日：2015-02-18

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Mari MATSUMOTO ,  Kosuke TATSUMURA ,  Shinichi YASUDA ,  Koichiro ZAITSU

    IPC: H03K19/173 ,  H03K19/0185

    CPC classification number: H03K19/1735 ,  H03K19/018585 ,  H03K19/1776

    Abstract: A nonvolatile programmable logic switch of an embodiment includes: a cell including: a first memory including a first terminal connected to a first wiring line, and a second terminal; a second memory including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory; a first transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and a second transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a gate of a pass transistor, and a gate is connected to a fifth wiring line.

    Abstract translation: 实施例的非易失性可编程逻辑开关包括：单元，包括：第一存储器，包括连接到第一布线的第一端子和第二端子; 第二存储器，包括连接到第二布线的第三端子和连接到第一存储器的第二端子的第四端子; 源极和漏极之一连接到第二和第四端子的第一晶体管，源极和漏极中的另一个连接到第三布线，栅极连接到第四布线; 以及第二晶体管，其源极和漏极中的一个连接到第二和第四端子，源极和漏极中的另一个连接到通过晶体管的栅极，栅极连接到第五布线 线。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140131811A1

    公开(公告)日：2014-05-15

    申请号：US14072948

    申请日：2013-11-06

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Masumi SAITOH ,  Kensuke OTA ,  Toshinori NUMATA ,  Chika TANAKA ,  Shinichi YASUDA ,  Kosuke TATSUMURA ,  Koichiro ZAITSU

    IPC: H01L27/11 ,  H01L27/12

    CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L27/1104

    Abstract: A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature.

    Abstract translation: 实施例的半导体器件包括：第一晶体管，具有布置在第一突出半导体区域中的第一源极区域和第一漏极区域，第一沟道区域在其上部中的与第一方向垂直的截面中具有第一角部 所述第一角部具有第一曲率半径; 第二晶体管，具有布置在第二突出半导体区域中的第二源极区域和第二漏极区域;以及第二沟道区域，所述第二沟道区域在其上部具有与第二方向垂直的截面中的第二角部， 具有大于第一曲率半径的第二曲率半径。

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