公开(公告)号：US09105584B2

公开(公告)日：2015-08-11

申请号：US14147360

申请日：2014-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Mitsuhiro Omura ,  Toshiyuki Sasaki ,  Tsubasa Imamura ,  Kazuhisa Matsuda

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.

Abstract translation: 根据一个实施例，制造半导体器件的方法包括：形成第一线图案，该第一线图案包括位于下层之上的第一膜，在第一膜的第一线图案的侧壁和顶表面上沉积第二膜， 第二膜，以消除第一膜的第一线图案的顶表面上的第二膜，并将第二膜留在第一膜的第一线图案的侧壁上，并且去除第一线图案以形成第二线图案 的第二个电影在底层之上。 在相同的等离子体处理装置内依次执行沉积第二膜，蚀刻第二膜并除去第一线图案。

公开(公告)号：US09111875B2

公开(公告)日：2015-08-18

申请号：US14202494

申请日：2014-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiroshi Yamamoto ,  Tsubasa Imamura ,  Hisataka Hayashi ,  Mitsuhiro Omura

IPC: B44C1/22 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3088 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.

Abstract translation: 根据一个实施例，图案形成方法包括在下层之上形成层。 该层包括嵌段共聚物。 该方法还包括通过相分离嵌段共聚物形成包含第一聚合物和第二相包含第二聚合物的第一相，并且通过使用包括一氧化碳的蚀刻气体干蚀刻该层来选择性地除去第一相。

公开(公告)号：US09502470B2

公开(公告)日：2016-11-22

申请号：US14642911

申请日：2015-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsushi Takahashi ,  Toshiyuki Sasaki ,  Tsubasa Imamura

IPC: H01L27/24 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L45/00 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/2481 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1675

Abstract: According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.

Abstract translation: 根据一个实施例，半导体存储器件包括：包括主表面的衬底; 具有导电性或半导电性的多个第一膜，所述第一膜设置在所述基板的上方并在相对于所述主表面倾斜的第一方向上延伸; 多个具有导电性的第二膜，所述第二膜设置在所述基板的上方，并且沿相对于所述主表面倾斜且与所述第一方向交叉的第二方向延伸; 以及设置在第一膜和第二膜的交叉部分中的多个存储膜。

公开(公告)号：US20140083977A1

公开(公告)日：2014-03-27

申请号：US14036588

申请日：2013-09-25

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akio UI ,  Hisataka Hayashi ,  Kazuhiro Tomioka ,  Hiroshi Yamamoto ,  Tsubasa Imamura

IPC: H01J37/04

CPC classification number: H01J37/32422 ,  H01J37/04 ,  H01J37/32091 ,  H01J37/3211 ,  H01J37/32165 ,  H01J37/3244 ,  H01J37/32568 ,  H01J37/32697 ,  H01J37/32715 ,  H01J37/32724 ,  H01J37/32834 ,  H01J2237/3341 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67069 ,  H01L21/6831 ,  H01L21/68764

Abstract: In one embodiment, a plasma processing apparatus includes: a chamber; an introducing part; a counter electrode; a high-frequency power source; and a plurality of low-frequency power sources. A substrate electrode is disposed in the chamber, a substrate is directly or indirectly placed on the substrate electrode, and the substrate electrode has a plurality of electrode element groups. The introducing part introduces process gas into the chamber. The high-frequency power source outputs a high-frequency voltage for ionizing the process gas to generate plasma. The plurality of low-frequency power sources apply a plurality of low-frequency voltages of 20 MHz or less with mutually different phases for introducing ions from the plasma, to each of the plurality of electrode element groups.

Abstract translation: 在一个实施例中，等离子体处理装置包括：腔室; 引进部分; 对电极 高频电源; 和多个低频电源。 衬底电极设置在腔室中，衬底直接或间接地放置在衬底电极上，并且衬底电极具有多个电极元件组。 引入部分将工艺气体引入腔室。 高频电源输出用于使工艺气体电离以产生等离子体的高频电压。 多个低频电源以相互不同的相位施加多个20MHz以下的低频电压，将等离子体的离子引入多个电极元件组。

公开(公告)号：US09373523B2

公开(公告)日：2016-06-21

申请号：US14616847

申请日：2015-02-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keisuke Kikutani ,  Tsubasa Imamura

IPC: H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/31122 ,  H01L21/3065

Abstract: A semiconductor device manufacturing method includes performing reactive ion etching of the film containing a metal disposed on the bottom of the first groove and the film containing a metal disposed on the bottom of the second groove under a same condition in a state where the substrate is heated to the target temperature.

Abstract translation: 一种半导体器件制造方法，包括在基板被加热的状态下，在相同的条件下对含有设置在第一槽的底部的金属的膜和含有设置在第二槽的底部的金属的膜进行反应离子蚀刻 达到目标温度。

公开(公告)号：US09384980B2

公开(公告)日：2016-07-05

申请号：US14481008

申请日：2014-09-09

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yasuhito Yoshimizu ,  Mitsuhiro Omura ,  Hisashi Okuchi ,  Satoshi Wakatsuki ,  Tsubasa Imamura

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/32139 ,  H01L21/76816

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.

Abstract translation: 根据实施例，半导体器件的制造方法包括：通过使用第一材料在处理对象上形成第一膜; 通过使用第二材料在所述第一膜上形成第二膜; 选择性地去除第二和第一膜以提供在第二和第一膜中刺穿的开口; 在第一膜的开口的内表面上选择性地形成金属膜; 并且通过使用金属膜作为掩模来处理处理目标。

公开(公告)号：US20160071739A1

公开(公告)日：2016-03-10

申请号：US14616847

申请日：2015-02-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keisuke KIKUTANI ,  Tsubasa Imamura

IPC: H01L21/311

CPC classification number: H01L21/31122 ,  H01L21/3065

Abstract: A semiconductor device manufacturing method includes performing reactive ion etching of the film containing a metal disposed on the bottom of the first groove and the film containing a metal disposed on the bottom of the second groove under a same condition in a state where the substrate is heated to the target temperature.

Abstract translation: 一种半导体器件制造方法，包括在基板被加热的状态下，在相同的条件下对含有设置在第一槽的底部的金属的膜和含有设置在第二槽的底部的金属的膜进行反应离子蚀刻 达到目标温度。

公开(公告)号：US20160035792A1

公开(公告)日：2016-02-04

申请号：US14642911

申请日：2015-03-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsushi TAKAHASHI ,  Toshiyuki Sasaki ,  Tsubasa Imamura

IPC: H01L27/24 ,  H01L21/311 ,  H01L45/00 ,  H01L21/308 ,  H01L21/28 ,  H01L27/115 ,  H01L21/3065

CPC classification number: H01L27/2481 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1675

Abstract: According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.

Abstract translation: 根据一个实施例，半导体存储器件包括：包括主表面的衬底; 具有导电性或半导电性的多个第一膜，所述第一膜设置在所述基板的上方并在相对于所述主表面倾斜的第一方向上延伸; 多个具有导电性的第二膜，所述第二膜设置在所述基板的上方，并且沿相对于所述主表面倾斜且与所述第一方向交叉的第二方向延伸; 以及设置在第一膜和第二膜的交叉部分中的多个存储膜。

公开(公告)号：US20150011089A1

公开(公告)日：2015-01-08

申请号：US14202494

申请日：2014-03-10

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hiroshi Yamamoto ,  Tsubasa Imamura ,  Hisataka Hayashi ,  Mitsuhiro Omura

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.

Abstract translation: 根据一个实施例，图案形成方法包括在下层之上形成层。 该层包括嵌段共聚物。 该方法还包括通过相分离嵌段共聚物形成包含第一聚合物和第二相包含第二聚合物的第一相，并且通过使用包括一氧化碳的蚀刻气体干蚀刻该层来选择性地除去第一相。