公开(公告)号：US20080195341A1

公开(公告)日：2008-08-14

申请号：US12105374

申请日：2008-04-18

申请人： Keith A. Jenkins ,  Seongwon Kim

发明人： Keith A. Jenkins ,  Seongwon Kim

IPC分类号： G01R29/02

CPC分类号： G01R31/3016

摘要： A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

摘要翻译： 提供了一种用于确定组件的延迟时间间隔的系统和方法。 该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。 该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

公开(公告)号：US07863918B2

公开(公告)日：2011-01-04

申请号：US11939145

申请日：2007-11-13

申请人： Keith A. Jenkins ,  Seongwon Kim

发明人： Keith A. Jenkins ,  Seongwon Kim

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  H01L22/20 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.

摘要翻译： 用于对三维集成电路的集成电路层进行自检的装置和方法包括在具有待测试的第一电路的共同衬底上一体地形成一次性自检电路。 第一电路形成三维集成电路结构的层。 第一个电路使用自检电路的电路进行测试。 通过从第一电路分离自检电路来去除自检电路。

公开(公告)号：US20090121736A1

公开(公告)日：2009-05-14

申请号：US11939145

申请日：2007-11-13

申请人： KEITH A. JENKINS ,  Seongwon Kim

发明人： KEITH A. JENKINS ,  Seongwon Kim

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  H01L22/20 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.

摘要翻译： 用于对三维集成电路的集成电路层进行自检的装置和方法包括在具有待测试的第一电路的共同衬底上一体地形成一次性自检电路。 第一电路形成三维集成电路结构的层。 第一个电路使用自检电路的电路进行测试。 通过从第一电路分离自检电路来去除自检电路。

公开(公告)号：US07378831B1

公开(公告)日：2008-05-27

申请号：US11624392

申请日：2007-01-18

申请人： Keith A. Jenkins ,  Seongwon Kim

发明人： Keith A. Jenkins ,  Seongwon Kim

IPC分类号： G01R19/00 ,  G01R29/02 ,  H03H11/26

CPC分类号： G01R31/3016

摘要： A system and a method for determining a delay time interval of components are provided. The system includes a delay chain of components having a plurality of components wherein each component of the delay chain of components has a first delay time interval. The system utilizes a reference clock signal to stimulate the delay change of components and monitors a delay clock signal output by the delay chain of components to determine a delay time interval associated with each component in the delay chain of components.

摘要翻译： 提供了一种用于确定组件的延迟时间间隔的系统和方法。 该系统包括具有多个部件的部件的延迟链，其中部件的延迟链的每个部件具有第一延迟时间间隔。 该系统利用参考时钟信号来刺激部件的延迟变化并且监视由部件的延迟链输出的延迟时钟信号，以确定与部件的延迟链中的每个部件相关联的延迟时间间隔。

公开(公告)号：US08824218B2

公开(公告)日：2014-09-02

申请号：US13552932

申请日：2012-07-19

申请人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

发明人： Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC分类号： G11C7/06

CPC分类号： G11C13/004 ,  G11C7/067 ,  G11C11/5678 ,  G11C13/0004

摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.

摘要翻译： 紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。 读出放大器读取存储单元的状态。 感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器 状态。

公开(公告)号：US08564262B2

公开(公告)日：2013-10-22

申请号：US12944392

申请日：2010-11-11

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Seongwon Kim

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Seongwon Kim

IPC分类号： G05G1/56

CPC分类号： G05F1/575 ,  G05F1/565

摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.

摘要翻译： 提供电源门控或旁路电压调节器的机制。 响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得 基本上没有电压被第一电路输出到主输出节点。 响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上 电压源的电压由第一电路输出到主输出节点。

公开(公告)号：US08351166B2

公开(公告)日：2013-01-08

申请号：US12508665

申请日：2009-07-24

申请人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

发明人： Howard H. Chen ,  Kai D. Feng ,  Louis L. Hsu ,  Seongwon Kim

IPC分类号： H01G7/16 ,  G01R31/12

CPC分类号： G01R31/024 ,  G01R31/028

摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.

摘要翻译： 一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。 每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。 泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。 如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。 可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

公开(公告)号：US20110161682A1

公开(公告)日：2011-06-30

申请号：US12650516

申请日：2009-12-30

申请人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

发明人： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3287 ,  Y02D10/171

摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.

摘要翻译： 电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。 第一调节器模块耦合到第一接口和第二接口。 第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。 向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。 接收的功率被调节以在第二电压下产生功率。 将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。 处理器接口向处理器的多个逻辑组的逻辑组递送电力。

公开(公告)号：US07855534B2

公开(公告)日：2010-12-21

申请号：US11847461

申请日：2007-08-30

申请人： Seongwon Kim

发明人： Seongwon Kim

IPC分类号： G05F1/595

CPC分类号： G05F1/467

摘要： A method for regulating a voltage using a linear voltage regulator is provided. The linear voltage regulator has a first circuit with a primary output node and a second circuit having first and second inverters electrically coupled to the primary output node. The method includes receiving a first voltage from a voltage source at the first circuit. The method further includes removing frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node utilizing the first circuit. The method further includes removing frequency components of the output voltage in a second frequency range utilizing the first and second inverters of the second circuit, the second frequency range being greater than the first frequency range.

摘要翻译： 提供一种使用线性电压调节器来调节电压的方法。 线性电压调节器具有具有主输出节点的第一电路和具有电耦合到主输出节点的第一和第二反相器的第二电路。 该方法包括从第一电路的电压源接收第一电压。 该方法还包括：在第一频率范围内去除第一电压的频率分量，以利用第一电​​路在主输出节点处获得输出电压。 该方法还包括利用第二电路的第一和第二反相器去除第二频率范围内的输出电压的频率分量，第二频率范围大于第一频率范围。

公开(公告)号：US20140063925A1

公开(公告)日：2014-03-06

申请号：US13434739

申请日：2012-03-29

申请人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

发明人： Daniel J. Friedman ,  Seongwon Kim ,  Yong Liu ,  Bipin Rajendran

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

摘要翻译： 本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。 每个相变存储单元耦合到相应的晶体管。 每个晶体管耦合到字线。 每个位线耦合到器件的相变存储器单元。 该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。 在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。 在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。