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    Memory device
    1.
    发明授权
    Memory device 有权

    公开(公告)号：US11495278B2

    公开(公告)日：2022-11-08

    申请号：US17201471

    申请日：2021-03-15

    Applicant: Kioxia Corporation

    Inventor： Yoshiaki Osada ,  Kosuke Hatsuda

    IPC: G11C11/16 ,  H01L27/22

    Abstract: According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.

    Semiconductor storage device
    2.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US10956092B2

    公开(公告)日：2021-03-23

    申请号：US16802454

    申请日：2020-02-26

    Applicant: KIOXIA CORPORATION

    Inventor： Yorinobu Fujino ,  Kosuke Hatsuda

    IPC: G11C7/00 ,  G06F3/06 ,  G11C8/14 ,  G11C8/10 ,  G11C17/18

    Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.

    Memory system
    3.
    发明授权
    Memory system 有权

    公开(公告)号：US12293096B2

    公开(公告)日：2025-05-06

    申请号：US17939848

    申请日：2022-09-07

    Applicant: Kioxia Corporation

    Inventor： Kosuke Hatsuda

    IPC: G11C11/00 ,  G06F3/06 ,  G11C11/16

    Abstract: A memory system includes a non-volatile memory and a memory controller configured to receive a command including an access target in the non-volatile memory and setting information from an external device and configured to control a writing operation or a reading operation to the access target. The memory controller has a condition setting circuit. The condition setting circuit is capable of performing the writing operation or the reading operation under a plurality of different conditions. The memory controller performs the writing operation or the reading operation under one of the plurality of different conditions selected by the condition setting circuit in accordance with the setting information.

    Memory device with switching element connected in series to resistance change memory element
    5.
    发明授权
    Memory device with switching element connected in series to resistance change memory element 有权

    公开(公告)号：US11386944B2

    公开(公告)日：2022-07-12

    申请号：US16821510

    申请日：2020-03-17

    Applicant: KIOXIA CORPORATION

    Inventor： Kosuke Hatsuda

    IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22

    Abstract: According to one embodiment, a memory device includes first and second wiring lines, a memory cell connected between the first and second wiring lines and including a resistance change memory element and a switching element connected in series to the resistance change memory element, and a determination circuit determining a determination object resistance state set in advance to the resistance change memory element based on a determination object voltage applied to the second wiring line when the switching element makes a transition from an on-state to an off-state.

    Memory system storing management information and method of controlling same
    8.
    发明授权
    Memory system storing management information and method of controlling same 有权

    公开(公告)号：US11573712B2

    公开(公告)日：2023-02-07

    申请号：US17229096

    申请日：2021-04-13

    Applicant: KIOXIA CORPORATION

    Inventor： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

    IPC: G06F3/06 ,  G06F11/14 ,  G11C7/20 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F12/02

    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

    Variable resistance memory device
    9.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US11508424B2

    公开(公告)日：2022-11-22

    申请号：US17198495

    申请日：2021-03-11

    Applicant: Kioxia Corporation

    Inventor： Kosuke Hatsuda

    IPC: G11C11/16

    Abstract: A first memory cell is coupled to first and third interconnects. A second memory cell is coupled to second and fourth interconnects. A first sense amplifier has a first terminal coupled to the first interconnect and a node of a first potential and a second terminal located close to a node of a second potential and coupled to the third interconnect and has a potential difference between the first and second terminals. A second sense amplifier has a third terminal coupled to the fourth interconnect and a node of a third potential and a fourth terminal located close to a node of a fourth potential and coupled to the second interconnect and has a potential difference between the third and fourth terminals.

    Semiconductor storage device and controlling method thereof
    10.
    发明授权
    Semiconductor storage device and controlling method thereof 有权

    公开(公告)号：US11501811B2

    公开(公告)日：2022-11-15

    申请号：US17350382

    申请日：2021-06-17

    Applicant: Kioxia Corporation

    Inventor： Kosuke Hatsuda

    IPC: G11C11/16 ,  G11C7/10

    Abstract: In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.

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