公开(公告)号：US20230189661A1

公开(公告)日：2023-06-15

申请号：US17898812

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Shogo ITAI ,  Kazuya MATSUZAWA ,  Masahiko NAKAYAMA ,  Hiroyuki KANAYA ,  Hideyuki SUGIYAMA

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  G11C5/08

CPC classification number: H01L43/10 ,  G11C5/08 ,  H01L27/222 ,  H01L43/02

Abstract: A switching element includes a first conductive layer, a second conductive layer, and a switching material layer provided between the first conductive layer and the second conductive layer and formed of an insulating material containing an additional element. The switching material layer includes a first interface region including a first interface between the first conductive layer and the switching material layer and a second interface region including a second interface between the second conductive layer and the switching material layer. A concentration of the additional element in the switching material layer has a first peak in the first interface region.

公开(公告)号：US20230079445A1

公开(公告)日：2023-03-16

申请号：US17692625

申请日：2022-03-11

Applicant: Kioxia Corporation

Inventor： Kenji FUKUDA ,  Hideyuki SUGIYAMA ,  Masahiko NAKAYAMA ,  Hiroyuki KANAYA ,  Soichi OIKAWA

IPC: H01L27/22

Abstract: According to one embodiment, a memory device includes a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a third memory cell adjacent to the first memory cell in a second direction, each of the first, second, and third memory cells including a resistance change memory element and a switching element. The switching element includes first and second electrodes, and a switching material layer between the first and second electrodes, the first and second electrodes overlap each other when viewed from the first direction, the first electrodes in the first and second memory cells are apart from each other, and the switching material layers in the first and second memory cells are continuously provided.

公开(公告)号：US20240428836A1

公开(公告)日：2024-12-26

申请号：US18746057

申请日：2024-06-18

Applicant: Kioxia Corporation

Inventor： Masahiko NAKAYAMA ,  Tatsuo SHIOZAWA

IPC: G11C11/16 ,  H10B61/00

Abstract: According to one embodiment, a memory system includes a memory unit including a memory cell array which includes a plurality of memory cells and which is divided into a plurality of memory cell blocks, and a drive circuit which drives the plurality of memory cells, and a controller which controls the memory unit. Each of the plurality of memory cells includes a resistance change memory element and a switching element connected in series to the resistance change memory element, and the controller is configured to control the memory unit in such a manner that the number of times of predetermined access to each of the plurality of memory cell blocks increases or decreases according to a distance from the drive circuit to each of the plurality of memory cell blocks.

公开(公告)号：US20240292631A1

公开(公告)日：2024-08-29

申请号：US18587939

申请日：2024-02-26

Applicant: Kioxia Corporation

Inventor： Hiroyuki KANAYA ,  Masahiko NAKAYAMA

IPC: H10B61/00

CPC classification number: H10B61/10

Abstract: A semiconductor storage device includes a plurality of first wirings extending in a first direction and a plurality of second wirings extending in a second direction intersecting the first direction. A plurality of memory cells are connected between the plurality of first wirings and the plurality of second wirings and include selectors each connected in series to variable resistance elements. Each selector includes a selector material switching a current flowing to the variable resistance element according to a voltage difference between the first wiring and the second wiring, and first and second electrodes sandwiching the selector material in a portion between the first wiring and the variable resistance element. A contact area between the first electrode and the selector material is less than an area of the selector material when viewed in a stacking direction of the selector and the variable resistance element.

公开(公告)号：US20230309428A1

公开(公告)日：2023-09-28

申请号：US17899914

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Kenji FUKUDA ,  Rina NOMOTO ,  Hiroyuki KANAYA ,  Masahiko NAKAYAMA ,  Hideyuki SUGIYAMA

IPC: H01L45/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L45/1286 ,  H01L45/1616 ,  H01L45/1675 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/161 ,  H01L27/222 ,  H01L27/2463

Abstract: A storage device includes a memory cell including a variable resistance element and a switching element having snapback current-voltage characteristics. The switching element includes a first conductive layer in contact with the variable resistance element, a second conductive layer, and a switching layer provided between the first conductive layer and the second conductive layer. The switching layer includes at least one switching member and a first insulating layer having a thermal conductivity higher than 1.4 W/m/K. A cross-sectional area of the switching member at a connection surface between the switching layer and the first conductive layer and a cross-sectional area of the switching member at a connection surface between the switching layer and the second conductive layer are each smaller than a cross-sectional area at a connection surface between the first conductive layer and the variable resistance element.

公开(公告)号：US20220301621A1

公开(公告)日：2022-09-22

申请号：US17461858

申请日：2021-08-30

Applicant: KIOXIA CORPORATION

Inventor： Masahiko NAKAYAMA ,  Kazumasa SUNOUCHI

IPC: G11C13/00

Abstract: A storage device includes a memory cell array in which a plurality of memory cells respectively including a variable resistance memory element are divided into a plurality of memory blocks, the plurality of memory cells including a first memory cell and a second memory cell that are in the same memory block, and a detection circuit. During a read operation in which the first memory cell is a read target, the detection circuit compares a first resistance value, which is a resistance value of the variable resistance memory element in the first memory cell, with a second resistance value, which is a resistance value of the variable resistance memory element in the second memory cell, and determines a value of data stored in the first memory cell based on whether or not the first resistance value is higher or lower than the second resistance value.

公开(公告)号：US20240090344A1

公开(公告)日：2024-03-14

申请号：US18178469

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Takeo KOIKE ,  Rina NOMOTO ,  Hiroyuki KANAYA ,  Masahiko NAKAYAMA ,  Daisuke WATANABE

IPC: H10N50/85 ,  H10B61/00 ,  H10N50/20

CPC classification number: H10N50/85 ,  H10B61/00 ,  H10N50/20 ,  H01F10/329

Abstract: A magnetic storage device includes first and second magnetic layers and a non-magnetic layer, where the non-magnetic layer includes a first oxide layer containing magnesium and oxygen, a second oxide layer containing magnesium and oxygen, a third oxide layer containing zinc and oxygen, a fourth oxide layer containing a first predetermined element and oxygen, and a fifth oxide layer containing a second predetermined element and oxygen, and a crystal structure of an oxide of the first predetermined element and a crystal structure of an oxide of the second predetermined element are each a rock salt structure. The first predetermined element and the second predetermined element each have an oxide formation free energy greater than an oxide formation free energy of zinc, and the oxide of the first predetermined element and the oxide of the second predetermined element each have a bandgap narrower than a bandgap of an oxide of magnesium.

公开(公告)号：US20230380183A1

公开(公告)日：2023-11-23

申请号：US18229133

申请日：2023-08-01

Applicant: Kioxia Corporation

Inventor： Masayoshi IWAYAMA ,  Tatsuya KISHI ,  Masahiko NAKAYAMA ,  Toshihiko NAGASE ,  Daisuke WATANABE ,  Tadashi KAI

IPC: H10B61/00 ,  H10N50/01

CPC classification number: H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.

公开(公告)号：US20220293171A1

公开(公告)日：2022-09-15

申请号：US17459467

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Masahiko NAKAYAMA ,  Kazumasa SUNOUCHI ,  Jyunichi OZEKI

IPC: G11C13/00 ,  G11C5/06

Abstract: According to one embodiment, a storage device includes first wirings extending in a first direction and second wirings extending in a second direction. A memory cells are connected between the first wirings and the second wirings and include a variable resistance memory element. A first drive circuit is provided for supplying voltages to the first wirings, and a second drive circuit is provided for supplying voltages to the second wirings. The first drive circuit applies a first voltage to a selected first wiring, the second drive circuit applies a second voltage to a selected second wiring. A voltage between the second voltage and one-half of the sum of the first and second voltages is applied to a non-selected first wiring, and a voltage between the first voltage and one-half of the sum of the first and second voltages is applied to a non-selected second wiring.

公开(公告)号：US20220278168A1

公开(公告)日：2022-09-01

申请号：US17750002

申请日：2022-05-20

Applicant: KIOXIA CORPORATION

Inventor： Masahiko NAKAYAMA ,  Kazumasa SUNOUCHI ,  Gaku SUDO ,  Tadashi KAI

IPC: H01L27/22 ,  H01L43/02

Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.