公开(公告)号：US20170141230A1

公开(公告)日：2017-05-18

申请号：US15267705

申请日：2016-09-16

申请人： Kabushiki Kaisha Toshiba

发明人： Keiji IKEDA ,  Shintaro Nakano ,  Yuya Maeda ,  Tomomasa Ueda ,  Kentaro Miura ,  Nobuyoshi Saito ,  Tsutomu Tezuka

IPC分类号： H01L29/786 ,  H01L29/24

CPC分类号： H01L29/7869 ,  H01L27/11573 ,  H01L27/1464 ,  H01L27/14643 ,  H01L29/24 ,  H01L29/78696

摘要： According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.

公开(公告)号：US20180033478A1

公开(公告)日：2018-02-01

申请号：US15445331

申请日：2017-02-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chika TANAKA ,  Keiji IKEDA ,  Toshinori NUMATA ,  Tsutomu TEZUKA

IPC分类号： G11C11/4091 ,  G11C14/00

CPC分类号： G11C11/4091 ,  G11C7/1048 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/565 ,  G11C14/0018 ,  G11C2207/002 ,  H01L27/10811

摘要： According to one embodiment, a semiconductor memory device includes a memory cell, the cell includes a first capacitor which includes first and second electrodes, and a first transistor which includes first and second terminals and a first control terminal, the first terminal being connected to the first electrode, a first conductive line connected to the second terminal, a second conductive line connected to the second electrode, a sense amplifier, a switch element connected between the first conductive line and the sense amplifier, and a controller turning off the switch element in a write operation, applies a first potential to the first conductive line, and sets a potential of the second conductive line according to a value of write data to be written to the cell.

公开(公告)号：US20170040377A1

公开(公告)日：2017-02-09

申请号：US15226276

申请日：2016-08-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Keiji IKEDA ,  Tsutomu TEZUKA

IPC分类号： H01L27/146

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14636

摘要： According to one embodiment, a sensing device includes a photodiode; a first transistor including a first terminal, a second terminal and a control terminal, the first terminal being connected to the photodiode; an electrode configured to detect a potential of the measurement target; a second transistor including a third terminal, a fourth terminal and a control terminal, the third terminal being connected to the electrode; and a charge storage connected to the second terminal of the first transistor and to the fourth terminal of the second transistor.

摘要翻译： 根据一个实施例，感测装置包括光电二极管; 第一晶体管，包括第一端子，第二端子和控制端子，所述第一端子连接到所述光电二极管; 电极，被配置为检测所述测量对象的电位; 第二晶体管，包括第三端子，第四端子和控制端子，所述第三端子连接到所述电极; 以及连接到第一晶体管的第二端子和第二晶体管的第四端子的电荷存储器。

公开(公告)号：US20160293583A1

公开(公告)日：2016-10-06

申请号：US15082546

申请日：2016-03-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chika TANAKA ,  Keiji IKEDA ,  Masumi SAITOH

IPC分类号： H01L25/065 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7855

摘要： A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of the n-channel transistor and the p-channel transistor being disposed above the other of the n-channel transistor and the p-channel transistor.

摘要翻译： 根据实施例的半导体集成电路包括：包括n沟道晶体管和p沟道晶体管的CMOS反相器，n沟道晶体管和p沟道晶体管中的一个设置在n沟道晶体管的另一个之上 和p沟道晶体管。

公开(公告)号：US20160268304A1

公开(公告)日：2016-09-15

申请号：US15067830

申请日：2016-03-11

申请人： Kabushiki Kaisha Toshiba

发明人： Keiji IKEDA ,  Masumi SAITOH ,  Hideaki AOCHI ,  Takeshi KAMIGAICHI ,  Jun FUJIKI

IPC分类号： H01L27/115 ,  H01L29/24 ,  H01L29/423 ,  H01L29/04 ,  H01L49/02 ,  H01L23/528 ,  H01L29/16

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

摘要翻译： 该非易失性半导体存储器件包括：包括存储单元的存储单元阵列; 以及将存储单元阵列连接到外部电路的布线部分。 存储单元阵列包括连接到存储单元并沿层叠方向布置的多个第一导电层。 另一方面，布线部分包括：沿层叠方向布置并分别连接到多个第一导电层的多个第二导电层，多个第二导电层的端部的位置在第一方向交叉处不同 堆叠方向; 从所述第二导电层沿层叠方向延伸的第三导电层; 连接到所述第三导电层的一端的沟道半导体层; 以及通过栅极绝缘膜设置在沟道半导体层的表面上的栅电极布线。

公开(公告)号：US20150102419A1

公开(公告)日：2015-04-16

申请号：US14577209

申请日：2014-12-19

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Keiji IKEDA ,  Tsutomu TEZUKA ,  Yuuichi KAMIMUTA ,  Kiyoe FURUSE

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/324

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78684 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体器件包括设置在半导体衬底上的第一互补半导体器件，并且包括CMOS电路，设置在第一互补半导体器件上方的金属电极，设置在金属电极上方的半导体层，包括nMOS区域 和pMOS区域彼此分离，并含有Ge; 以及包括设置在半导体层的第一部分上的nMOSFET和设置在半导体层的第二部分上的pMOSFET的第二互补半导体器件。

公开(公告)号：US20190088288A1

公开(公告)日：2019-03-21

申请号：US15897596

申请日：2018-02-15

申请人： Kabushiki Kaisha Toshiba

发明人： Kosuke TATSUMURA ,  Keiji IKEDA ,  Tsutomu TEZUKA

IPC分类号： G11C5/06 ,  H01L29/786 ,  G11C11/40

摘要： According to an embodiment, a semiconductor device includes a plurality of first interconnections, a plurality of gate dielectric films, and a plurality of second interconnections. The plurality of first interconnections are oxide semiconductors formed in parallel at predetermined intervals in a first direction. The plurality of gate dielectric films are formed on surfaces of the first interconnections, respectively. The plurality of second interconnections are conductors formed at predetermined intervals in parallel to a second direction orthogonal to the first direction, respectively, to bridge over the gate dielectric films.

公开(公告)号：US20170271341A1

公开(公告)日：2017-09-21

申请号：US15266798

申请日：2016-09-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chika TANAKA ,  Keiji IKEDA ,  Yoshihiro UEDA ,  Toshinori NUMATA ,  Tsutomu TEZUKA

IPC分类号： H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  G11C11/408 ,  G11C11/4091 ,  H01L29/24

CPC分类号： H01L27/10897 ,  G11C5/025 ,  G11C11/404 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/1082 ,  H01L29/24 ,  H01L29/7827

摘要： According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode, and a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier.

公开(公告)号：US20170074822A1

公开(公告)日：2017-03-16

申请号：US15235421

申请日：2016-08-12

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuya MATSUZAWA ,  Keiji IKEDA ,  Tsutomu TEZUKA

IPC分类号： G01N27/414 ,  H01L29/792

CPC分类号： G01N27/4148 ,  G01N27/333 ,  H01L29/792

摘要： An electrochemical sensor according to an embodiment, includes a first insulating film, an electrode, a semiconductor layer provided between the first insulating film and the electrode, and a charge storage layer provided between the electrode and the semiconductor layer.

摘要翻译： 根据实施例的电化学传感器包括第一绝缘膜，电极，设置在第一绝缘膜和电极之间的半导体层以及设置在电极和半导体层之间的电荷存储层。

公开(公告)号：US20160322353A1

公开(公告)日：2016-11-03

申请号：US15205484

申请日：2016-07-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Keiji IKEDA ,  Tsutomu TEZUKA

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L27/088 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1229 ,  H01L29/0649 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/7869

摘要： According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.

摘要翻译： 根据一个实施例，一种半导体器件包括：第一半导体层; 以及多个第一晶体管，包括设置在所述第一半导体层上的多个第一栅极结构，设置在所述第一半导体层中并位于所述第一栅极结构之下的第一沟道区，以及设置在所述第一半导体层中的多个第一扩散区 以夹住第一通道区域的方式。