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    Multilayered resist systems using tuned polymer films as underlayers and methods of fabrication thereof
    3.
    发明授权
    Multilayered resist systems using tuned polymer films as underlayers and methods of fabrication thereof 有权
    使用调谐聚合物膜作为底层的多层抗蚀剂系统及其制造方法

    公开(公告)号：US07361444B1

    公开(公告)日：2008-04-22

    申请号：US09256034

    申请日：1999-02-23

    申请人： Marie Angelopoulos ,  Katherina E. Babich ,  Douglas Charles LaTulipe ,  Qinghuang Lin ,  David R. Medeiros ,  Wayne Martin Moreau ,  Karen E. Petrillo ,  John P. Simons

    发明人： Marie Angelopoulos ,  Katherina E. Babich ,  Douglas Charles LaTulipe ,  Qinghuang Lin ,  David R. Medeiros ,  Wayne Martin Moreau ,  Karen E. Petrillo ,  John P. Simons

    IPC分类号： G03F7/023

    CPC分类号： G03F7/091 ,  Y10S430/145

    摘要： Disclosed are multilayered resist structures including bilayer and top surface imaging which utilize tuned underlayers functioning as ARCs, planarizing layers, and etch resistant hard masks whose properties such as optical, chemical and physical properties are tailored to give a multilayer resist structure exhibiting high resolution, residue free lithography and methods of preparing these materials. These underlayer films include the group consisting of novolac based resists whose processing conditions are controlled, polyarylsulfones such as the BARL material, polyhydroxystyrene based derivatives, an example being a copolymer of polyhydroxystyrene and polyhydroxystyrene reacted with anthracenemethanol that contains a cross-linker, and acid catalyst (thermal acid generator), polyimides, polyethers in particular polyarylene ethers, polyarylenesulfides, polycarbonates such as polyarylenecarbonates, epoxies, epoxyacrylates, polyarylenes such as polyphenylenes, polyarylenevinylenes such as polyphenylenevinylenes, polyvinylcarbazole, cyclicolefins, and polyesters. Such films have index of refraction and extinction coefficient tunable from about 1.4 to about 2.1 and from about 0.1 to about 0.6 at UV and DUV wavelengths, in particular 365, 248, 193 and 157 nm and EUV. Moreover, underlayer films produced in the present invention do not interact with the resist limiting interfacial mixing and contamination of resist by an outgassing product. The bilayer and TSI resist structures can be used for 248, 193, 157, EUV, x-ray, e-beam, and ion beam technology.

    摘要翻译： 公开了包括双层和顶面成像的多层抗蚀剂结构，其利用用作ARC的调谐底层，平坦化层和耐蚀刻硬掩模，其特性如光学，化学和物理性质被定制以产生呈现高分辨率的多层抗蚀剂结构 自由光刻及其制备方法。 这些下层膜包括其加工条件被控制的基于酚醛清漆的抗蚀剂的组，诸如BARL材料的聚芳基砜，聚羟基苯乙烯基衍生物，作为与含有交联剂的蒽甲醇反应的聚羟基苯乙烯和聚羟基苯乙烯的共聚物的实例，以及酸催化剂 （热酸生成剂），聚酰亚胺，聚醚，特别是聚亚芳基醚，聚芳基硫醚，聚碳酸酯如聚芳基碳酸酯，环氧化物，环氧丙烯酸酯，聚亚芳基如聚苯撑，聚亚芳基亚乙烯基如聚亚苯基亚乙烯基，聚乙烯基咔唑，环烯烃和聚酯。 这种膜的折射率和消光系数在UV和DUV波长，特别是365,248,293和157nm以及EUV下可调节为约1.4至约2.1和约0.1至约0.6。 此外，在本发明中制备的底层膜不与抗蚀剂界面混合和除气产物对抗蚀剂的污染相互作用。 双层和TSI抗蚀剂结构可用于248,193,157，EUV，X射线，电子束和离子束技术。

    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING
    7.
    发明申请
    SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING 审中-公开
    选择性外来成长通过孵化时间工程

    公开(公告)号：US20120295417A1

    公开(公告)日：2012-11-22

    申请号：US13109567

    申请日：2011-05-17

    申请人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    发明人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

    摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

    摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

    Method for tuning epitaxial growth by interfacial doping and structure including same
    10.
    发明授权
    Method for tuning epitaxial growth by interfacial doping and structure including same 有权
    通过界面掺杂和包括其的结构来调谐外延生长的方法

    公开(公告)号：US07329596B2

    公开(公告)日：2008-02-12

    申请号：US11259654

    申请日：2005-10-26

    申请人： Katherina E. Babich ,  Bruce B. Doris ,  David R. Medeiros ,  Devendra K. Sadana

    发明人： Katherina E. Babich ,  Bruce B. Doris ,  David R. Medeiros ,  Devendra K. Sadana

    IPC分类号： H01L21/44

    CPC分类号： H01L29/0847 ,  H01L21/2236 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7834

    摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.

    摘要翻译： 允许通过新颖的表面制备方案不使衬底变薄的不同掺杂的半导体表面（n型和p型）上的半导体材料均匀地同时外延生长的方法，以及由 提供了将该方案实现为集成电路的过程集成流程。 本发明的方法可以用于从不同的表面进行半导体材料的选择性或非选择性外延生长。 更具体地说，本发明包括一种在卤素和/或延伸注入过程期间用于对硅电路的n-FET和/或p-FET区进行反掺杂的方法，利用这样的技术，使两个区域的表面特性相对于 它们对湿表面或干表面制备的反应，并且使得两个先前不同的表面可以容易地升高的源极/漏极结构的同时外延生长; 但不会影响所得设备的电气性能。