Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory
    2.
    发明授权
    Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory 失效
    铁电电容器的制造方法及其制造方法

    公开(公告)号:US06297085B1

    公开(公告)日:2001-10-02

    申请号:US08988687

    申请日:1997-12-11

    IPC分类号: H01L218242

    摘要: To provide a method that can be used to form a high-qualility ferroelectric film by forming good nuclei when using the sputtering method to manufacture a PZT capacitor or other forroelectric capacitors using Ir or other electrode substances in addition to Pt for the electrode. In the method for manufacturing a PZT ferroelectric capacitor CAP, after titanium film 31 is deposited on Ir electrode 6, lead oxide 32 is deposited at a substrate temperature higher than the crystallization temperature of lead titanate using the sputtering method. Lead zirconate titanate 34 is then deposited at a substrate temperature higher than the aforementioned substrate temperature using the sputtering temperature. Afterwards, a heat treatment of the deposited film is performed to produce PZT film 17.

    摘要翻译: 为了提供一种方法,当使用溅射方法制造PZT电容器或使用Ir或其它电极物质的其它电介质电容器或除电极用Pt之外的其他电介质电容器时,可以通过形成良好的核来形成高质量铁电体膜。 在制造PZT铁电体电容器CAP的方法中,在氧化钛电极6上沉积钛膜31之后,使用溅射法在高于钛酸铅的结晶温度的衬底温度下沉积氧化铅32。 然后使用溅射温度在高于上述衬底温度的衬底温度下沉积锆钛酸铅34。 然后,进行沉积膜的热处理以产生PZT膜17。

    Method for manufacturing dielectric capacitor, dielectric memory device
    5.
    发明授权
    Method for manufacturing dielectric capacitor, dielectric memory device 失效
    介质电容器的制造方法,介质存储器件

    公开(公告)号:US6033953A

    公开(公告)日:2000-03-07

    申请号:US991132

    申请日:1997-12-16

    摘要: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

    摘要翻译: 提供了具有减小的漏电流的介质电容器。 对电容器的第一电极(38)的表面进行电解抛光,并在其上依次层压电介质膜(40)和第二电极(37)。 存在于第一电极表面上的凸部尖端(38a)通过电解抛光溶解而形成非常细微的抛光,形成曲面半径扩大的球面曲面,第一电极的表面 扁平化 因此,在第一电极和电介质膜的界面的操作期间可以防止电解浓度,并且可以显着降低泄漏电流。

    Method for forming high dielectric capacitor electrode structure and
semiconductor memory devices
    6.
    发明授权
    Method for forming high dielectric capacitor electrode structure and semiconductor memory devices 失效
    高介电电容电极结构和半导体存储器件的形成方法

    公开(公告)号:US5793600A

    公开(公告)日:1998-08-11

    申请号:US545980

    申请日:1995-10-20

    IPC分类号: H01L21/02 H01G4/06 H01G7/00

    摘要: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

    摘要翻译: 包括具有主要组分(Pb)和次要组分(Ti)的PZT铁电层17的电容器和电极结构,形成在铁电层的下侧上并由特殊元素(Pt)和Ti构成的下电极层16 ,及其化合物,以及扩散阻挡层18,其形成在下电极层的下侧,并且用作相对于Pb的扩散阻挡层。 可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动,以保持PZT铁电层的预期性能,从而简化和稳定 薄膜制造,并防止电气特性的劣化和对较低层的不利影响。

    Capacitor, electrode structure, and semiconductor memory device
    7.
    发明授权
    Capacitor, electrode structure, and semiconductor memory device 失效
    电容器,电极结构和半导体存储器件

    公开(公告)号:US5508953A

    公开(公告)日:1996-04-16

    申请号:US242924

    申请日:1994-05-16

    CPC分类号: H01L28/55 H01L28/60 H01L28/75

    摘要: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

    摘要翻译: 包括具有主要组分(Pb)和次要组分(Ti)的PZT铁电层17的电容器和电极结构,形成在铁电层的下侧上并由特殊元素(Pt)和Ti构成的下电极层16 ,及其化合物,以及扩散阻挡层18,其形成在下电极层的下侧,并且用作相对于Pb的扩散阻挡层。 可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动,以保持PZT铁电层的预期性能,从而简化和稳定 薄膜制造,并防止电气特性的劣化和对较低层的不利影响。

    Dummy cell structure for 1T1C FeRAM cell array

    公开(公告)号:US06721200B2

    公开(公告)日:2004-04-13

    申请号:US10397909

    申请日:2003-03-26

    IPC分类号: G11C1122

    CPC分类号: G11C11/22 G11C7/14

    摘要: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

    Method for fabricating reliable multilayer bottom electrode for ferroelectric capacitors
    9.
    发明授权
    Method for fabricating reliable multilayer bottom electrode for ferroelectric capacitors 有权
    制造可靠的铁电电容器多层底电极的方法

    公开(公告)号:US06238932B1

    公开(公告)日:2001-05-29

    申请号:US09231023

    申请日:1999-01-14

    IPC分类号: H01E706

    摘要: A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).

    摘要翻译: 一种强电介质电容器电极接触结构,包括放置在衬底(2)上并且在衬底(2)和绝缘体(4)之间包含晶体管源(6)和晶体管漏极(8)的绝缘体(4)。 绝缘体(4)包含源极插头(10)和导电排放塞(12)。 晶体管源(6)电连接到源极(10)。 晶体管漏极(8)电连接到导电排放塞(12)。 晶体管栅极(14)位于源极插头(10)和导电排放塞(12)之间,并被绝缘体(4)容纳。 金属布线(16)电连接到源插头(10)。 隔离膜(18)放置在绝缘体(4)和导电排放塞(12)之上。 底部电极(20)放置在阻挡膜(18)上方。 铁电层(22)放置在底部电极(20)上。 顶部电极(24)被放置在铁电层(22)上方。

    Method for forming a ferroelectric material film by the sol-gel method,
along with a process for a production of a capacitor and its raw
material solution
    10.
    发明授权
    Method for forming a ferroelectric material film by the sol-gel method, along with a process for a production of a capacitor and its raw material solution 失效
    通过溶胶 - 凝胶法形成铁电体膜的方法以及电容器及其原料溶液的制造方法

    公开(公告)号:US5840615A

    公开(公告)日:1998-11-24

    申请号:US810201

    申请日:1997-03-03

    摘要: A method for forming a ferroelectric material film, more particularly a lead zirconate titanate (PZT) film by the sol-gel method wherein a lowered oxidative sintering temperature may be adopted in preparing the ferroelectric material film with a perovskite crystalline structure, thereby reducing the risk of oxidation of metal electrodes and other circuits when the ferroelectric material film is employed as a dielectric in semiconductor devices, such as in a capacitor, for example. The method contemplates the preparation of a raw material solution containing an organometallic compound of a metallic element forming the ferroelectric material film, alkanolamine and/or stabilizer comprising a .beta.-diketone, with the concentration of the stabilizer being sufficient to provide a mole ratio to the total metal atoms of (stabilizer/total metal atoms)>3. The method then involves coating the raw material solution, drying the coated raw material solution to form a dried film, and sintering the dried film to form the ferroelectric material film wherein the oxidative sintering is carried out at a relatively low temperature of about 450.degree. C. in forming the ferroelectric material film with a perovskite crystalline structure.

    摘要翻译: 通过溶胶 - 凝胶法形成铁电材料膜的方法,特别是锆钛酸铅(PZT)薄膜,其中在制备具有钙钛矿晶体结构的铁电材料膜时可以采用降低的氧化烧结温度,从而降低风险 当将铁电材料膜用作例如电容器等半导体器件中的电介质时,金属电极和其他电路的氧化。 该方法考虑了制备含有形成铁电材料膜的金属元素的有机金属化合物的原料溶液,包含β-二酮的链烷醇胺和/或稳定剂,其稳定剂的浓度足以提供与 (稳定剂/总金属原子)的总金属原子> 3。 然后,该方法包括涂覆原料溶液,干燥涂覆的原料溶液以形成干燥膜,并烧结干燥的膜以形成铁电材料膜,其中氧化烧结在约450℃的较低温度下进行 在形成具有钙钛矿晶体结构的铁电材料膜时。