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公开(公告)号：US20080023846A1
公开(公告)日：2008-01-31
申请号：US11878796
申请日：2007-07-26
IPC分类号： H01L21/311 , H01L21/302 , H01L23/48
CPC分类号： H01L21/3065 , H01L21/30655 , H01L21/31138 , H01L21/76898 , H01L2224/02372 , H01L2224/05008 , H01L2224/05009 , H01L2224/05025 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2224/16 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/0494
摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.
摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。
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公开(公告)号：US08669183B2
公开(公告)日：2014-03-11
申请号：US11802107
申请日：2007-05-18
IPC分类号： H01L21/302
CPC分类号： H01L21/30655 , H01L21/76898 , H01L2224/02372 , H01L2224/05548 , H01L2924/0002 , H01L2924/00
摘要： This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.
摘要翻译： 本发明涉及在使用博世工艺的半导体器件中形成的通孔中形成均匀的膜。 穿过半导体衬底中的预定区域的通孔是通过使用掩模层作为掩模的博世工艺将半导体衬底从其表面之一蚀刻到另一表面而形成的。 接下来，去除掩模层。 然后，通过干法蚀刻除去扇贝，使通孔的侧壁变平。 接下来，在通孔中均匀地形成绝缘膜，阻挡层等。
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公开(公告)号：US08173543B2
公开(公告)日：2012-05-08
申请号：US11878796
申请日：2007-07-26
IPC分类号： H01L21/44 , H01L21/311
CPC分类号： H01L21/3065 , H01L21/30655 , H01L21/31138 , H01L21/76898 , H01L2224/02372 , H01L2224/05008 , H01L2224/05009 , H01L2224/05025 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2224/16 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/0494
摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.
摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。
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公开(公告)号：US20070281474A1
公开(公告)日：2007-12-06
申请号：US11802107
申请日：2007-05-18
IPC分类号： H01L21/3065
CPC分类号： H01L21/30655 , H01L21/76898 , H01L2224/02372 , H01L2224/05548 , H01L2924/0002 , H01L2924/00
摘要： This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.
摘要翻译： 本发明涉及在使用博世工艺的半导体器件中形成的通孔中形成均匀的膜。 穿过半导体衬底中的预定区域的通孔是通过使用掩模层作为掩模的博世工艺将半导体衬底从其表面之一蚀刻到另一表面而形成的。 接下来，去除掩模层。 然后，通过干法蚀刻除去扇贝，使通孔的侧壁变平。 接下来，在通孔中均匀地形成绝缘膜，阻挡层等。
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公开(公告)号：US08227901B2
公开(公告)日：2012-07-24
申请号：US12482674
申请日：2009-06-11
申请人： Katsuyuki Seki , Akira Suzuki , Keita Odajima , Kikuo Okada , Koujiro Kameyama
发明人： Katsuyuki Seki , Akira Suzuki , Keita Odajima , Kikuo Okada , Koujiro Kameyama
IPC分类号： H01L29/06
CPC分类号： H01L29/861 , H01L29/0649 , H01L29/6609
摘要： This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment. As a result, the inner wall of the mesa groove corresponding to the PN junction is covered with the second insulation film thick enough to secure a desired withstand voltage and to reduce a leakage current.
摘要翻译： 本发明的目的在于解决台面型半导体器件的问题，这是由于对应于PN结的台面槽的内壁上的第二绝缘膜的厚度减小导致的耐电压劣化和漏电流的发生， 并提供高耐受电压和高可靠性的台面型半导体器件及其制造方法。 在通过干蚀刻形成台面凹槽之后，用包含氢氟酸和硝酸的蚀刻溶液进行湿蚀刻，进一步施加到台面凹槽的侧壁上，以形成由第一绝缘膜上方形成的悬垂 台面凹槽 突出端用作防止形成在台面槽中的第二绝缘膜和围绕突出部分的区域的第一绝缘膜上的第一绝缘膜从底面凹槽的底部流出，这是由于由于 后续热处理。 结果，对应于PN结的台面凹槽的内壁被足够厚的第二绝缘膜覆盖以确保期望的耐受电压并减少漏电流。
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公开(公告)号：US08362595B2
公开(公告)日：2013-01-29
申请号：US12338686
申请日：2008-12-18
申请人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
发明人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
IPC分类号： H01L29/06 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N− type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
摘要翻译： 本发明提供一种台面半导体器件及其制造方法，其使制造成本最小化并防止器件的污染和物理损坏。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上进一步形成阳极，以连接到P型半导体层，并且从比N型半导体层更深的P型半导体层的前表面形成台面槽，以便 以包围阳极电极。 然后，从台面槽的内侧形成第二绝缘膜至阳极电极的端部。 第二绝缘膜由聚酰亚胺树脂等有机绝缘体构成。 然后将由半导体衬底制成的层压体和层压在其上的层沿划线切割。
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公开(公告)号：US08319317B2
公开(公告)日：2012-11-27
申请号：US12481292
申请日：2009-06-09
申请人： Katsuyuki Seki , Naofumi Tsuchiya , Akira Suzuki , Kikuo Okada
发明人： Katsuyuki Seki , Naofumi Tsuchiya , Akira Suzuki , Kikuo Okada
IPC分类号： H01L23/58
CPC分类号： H01L21/8222 , H01L21/02118 , H01L21/312 , H01L21/31662 , H01L27/0814 , H01L2924/10155
摘要： Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N− type semiconductor layer and the thermal oxide film. With the structure described above, an influence of the positive electric charges in the thermal oxide film is weakened and an extension of a depletion layer into the N− type semiconductor layer at the interface with the thermal oxide film is secured.
摘要翻译： 使用便宜的材料来解决传统的台面型半导体器件的问题，其中耐腐蚀性劣化和由与PN结相对应的台面凹槽的内壁上的绝缘膜的厚度减小引起的漏电流的发生 并且提供具有高耐压和高可靠性的台面型半导体器件及其制造方法。 在台面型半导体器件的台面槽的内壁上形成由热氧化膜制成的稳定的保护膜，以覆盖和保护PN结，形成具有负电荷的绝缘膜以填充 用热氧化膜覆盖的台面槽，使得在N-型半导体层和热氧化膜之间的界面处不容易形成电子蓄积层。 利用上述结构，确保了热氧化膜中的正电荷的影响，确保了与热氧化膜的界面处的耗尽层向N型半导体层的延伸。
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公开(公告)号：US08426949B2
公开(公告)日：2013-04-23
申请号：US12354620
申请日：2009-01-15
申请人： Katsuyuki Seki , Akira Suzuki , Keita Odajima
发明人： Katsuyuki Seki , Akira Suzuki , Keita Odajima
IPC分类号： H01L29/06
CPC分类号： H01L29/861 , H01L29/0603 , H01L29/0661
摘要： A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N−-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N−-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N−-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.
摘要翻译： 提供台面型半导体器件及其制造方法以增加耐受电压以及减少漏电流。 在半导体衬底的表面上形成N型半导体层，在N型半导体层上形成P型半导体层。 之后，通过蚀刻P型半导体层，PN结，N型半导体层和半导体衬底的局部厚度来形成台面凹槽，使得台面凹槽的宽度从 P型半导体层朝向半导体基板。 随后的湿法蚀刻除去由前述蚀刻引起的台面凹槽的内壁中的损伤层，并且在接近P型半导体层的表面的区域中转换台面槽，使得台面凹槽的宽度朝向 P型半导体层的表面。 之后，半导体衬底和堆叠在其上的层被切割。
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公开(公告)号：US08368181B2
公开(公告)日：2013-02-05
申请号：US12338694
申请日：2008-12-18
申请人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
发明人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
IPC分类号： H01L29/06 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/8613 , H01L29/6609
摘要： The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N− type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
摘要翻译： 本发明提供一种提高产量和生产率的台面半导体器件及其制造方法。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上进一步形成阳极，以连接到P型半导体层，并且从比N型半导体层更深的P型半导体层的表面形成台面槽，以便 以包围阳极电极。 然后，从台面槽的内侧形成第二绝缘膜到台面槽的外侧的P型半导体层上。 第二绝缘膜由聚酰亚胺树脂等有机绝缘体构成。 然后将由半导体衬底制成的层压体和层压在其上的层沿划线切割。
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公开(公告)号：US20090160034A1
公开(公告)日：2009-06-25
申请号：US12338686
申请日：2008-12-18
申请人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
发明人： Akira Suzuki , Katsuyuki Seki , Keita Odajima
IPC分类号： H01L29/06 , H01L21/441
CPC分类号： H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a mesa semiconductor device and a method of manufacturing the same which minimize the manufacturing cost and prevents contamination and physical damage of the device. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N− type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the end portion of the anode electrode. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
摘要翻译： 本发明提供一种台面半导体器件及其制造方法，其使制造成本最小化并防止器件的污染和物理损坏。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上进一步形成阳极，以连接到P型半导体层，并且从比N型半导体层更深的P型半导体层的前表面形成台面槽，以便 以包围阳极电极。 然后，从台面槽的内侧形成第二绝缘膜至阳极电极的端部。 第二绝缘膜由聚酰亚胺树脂等有机绝缘体构成。 然后将由半导体衬底制成的层压体和层压在其上的层沿划线切割。
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