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公开(公告)号：US09779965B2
公开(公告)日：2017-10-03
申请号：US15456767
申请日：2017-03-13
IPC分类号： H01L21/449 , H01L23/00 , H01L25/00 , H01L25/065 , H01L21/762 , H01L21/60
CPC分类号： H01L21/449 , H01L21/76251 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/75 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2021/60195 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13187 , H01L2224/136 , H01L2224/13687 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/48091 , H01L2224/48225 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75343 , H01L2224/75348 , H01L2224/75349 , H01L2224/75744 , H01L2224/75745 , H01L2224/759 , H01L2224/81121 , H01L2224/81193 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81355 , H01L2224/81409 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81801 , H01L2224/81895 , H01L2224/81906 , H01L2224/94 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20301 , H01L2924/20302 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20306 , H01L2924/20307 , H01L2924/01029 , H01L2924/01014 , H01L2924/00012 , H01L2924/014 , H01L2224/8121 , H01L2924/00 , H01L2224/45099 , H01L2224/81 , H01L2924/04941 , H01L2924/04953 , H01L2924/0503 , H01L2924/01013 , H01L2924/0504 , H01L2924/0105 , H01L2924/0502 , H01L2924/0103 , H01L2924/0494 , H01L2924/0104 , H01L2924/0495 , H01L2924/01023 , H01L2924/0496 , H01L2924/01024 , H01L2924/05 , H01L2924/01028 , H01L2924/0543 , H01L2924/0544 , H01L2924/0542 , H01L2924/0534 , H01L2924/0535 , H01L2924/0536 , H01L2924/054 , H01L2924/0463 , H01L2924/0464 , H01L2924/0462 , H01L2924/0454 , H01L2924/0455 , H01L2924/0456 , H01L2924/046 , H01L2924/01105
摘要： A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.
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公开(公告)号：US20170186627A1
公开(公告)日：2017-06-29
申请号：US15456767
申请日：2017-03-13
IPC分类号： H01L21/449 , H01L21/762 , H01L25/00 , H01L25/065 , H01L23/00
CPC分类号： H01L21/449 , H01L21/76251 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/75 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2021/60195 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13187 , H01L2224/136 , H01L2224/13687 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/48091 , H01L2224/48225 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75343 , H01L2224/75348 , H01L2224/75349 , H01L2224/75744 , H01L2224/75745 , H01L2224/759 , H01L2224/81121 , H01L2224/81193 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81355 , H01L2224/81409 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81801 , H01L2224/81895 , H01L2224/81906 , H01L2224/94 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20301 , H01L2924/20302 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20306 , H01L2924/20307 , H01L2924/01029 , H01L2924/01014 , H01L2924/00012 , H01L2924/014 , H01L2224/8121 , H01L2924/00 , H01L2224/45099 , H01L2224/81 , H01L2924/04941 , H01L2924/04953 , H01L2924/0503 , H01L2924/01013 , H01L2924/0504 , H01L2924/0105 , H01L2924/0502 , H01L2924/0103 , H01L2924/0494 , H01L2924/0104 , H01L2924/0495 , H01L2924/01023 , H01L2924/0496 , H01L2924/01024 , H01L2924/05 , H01L2924/01028 , H01L2924/0543 , H01L2924/0544 , H01L2924/0542 , H01L2924/0534 , H01L2924/0535 , H01L2924/0536 , H01L2924/054 , H01L2924/0463 , H01L2924/0464 , H01L2924/0462 , H01L2924/0454 , H01L2924/0455 , H01L2924/0456 , H01L2924/046 , H01L2924/01105
摘要： A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.
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公开(公告)号：US08173543B2
公开(公告)日：2012-05-08
申请号：US11878796
申请日：2007-07-26
IPC分类号： H01L21/44 , H01L21/311
CPC分类号： H01L21/3065 , H01L21/30655 , H01L21/31138 , H01L21/76898 , H01L2224/02372 , H01L2224/05008 , H01L2224/05009 , H01L2224/05025 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2224/16 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/0494
摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.
摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。
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公开(公告)号：US08072067B2
公开(公告)日：2011-12-06
申请号：US12436266
申请日：2009-05-06
IPC分类号： H01L23/48
CPC分类号： H01L23/525 , H01L23/53223 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/11462 , H01L2224/13024 , H01L2224/13144 , H01L2224/16225 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/15788 , H01L2924/3651 , H01L2924/01014 , H01L2924/04941 , H01L2924/01022 , H01L2924/00014 , H01L2924/0496 , H01L2924/0498 , H01L2924/0499 , H01L2924/0494 , H01L2924/04953 , H01L2924/00
摘要： A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.
摘要翻译： 提供了包括衬底，绝缘层，复合衬垫结构，钝化层和凸块的半导体结构。 电路结构设置在基板上。 绝缘层覆盖基板并且具有暴露电路结构的第一开口。 复合焊盘结构包括依次布置的第一导电层，阻挡层和第二导电层。 复合焊盘结构设置在绝缘层上并填充第一开口以电连接到电路结构。 钝化层覆盖复合焊盘结构，并具有露出复合焊盘结构的第二开口。 凸块填充第二开口并电连接到复合垫结构。
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公开(公告)号：US20100283146A1
公开(公告)日：2010-11-11
申请号：US12436266
申请日：2009-05-06
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/525 , H01L23/53223 , H01L24/02 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0231 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/11462 , H01L2224/13024 , H01L2224/13144 , H01L2224/16225 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01044 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/15788 , H01L2924/3651 , H01L2924/01014 , H01L2924/04941 , H01L2924/01022 , H01L2924/00014 , H01L2924/0496 , H01L2924/0498 , H01L2924/0499 , H01L2924/0494 , H01L2924/04953 , H01L2924/00
摘要： A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.
摘要翻译： 提供了包括衬底，绝缘层，复合衬垫结构，钝化层和凸块的半导体结构。 电路结构设置在基板上。 绝缘层覆盖基板并且具有暴露电路结构的第一开口。 复合焊盘结构包括依次布置的第一导电层，阻挡层和第二导电层。 复合焊盘结构设置在绝缘层上并填充第一开口以电连接到电路结构。 钝化层覆盖复合焊盘结构，并具有露出复合焊盘结构的第二开口。 凸块填充第二开口并电连接到复合垫结构。
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公开(公告)号：US20080023846A1
公开(公告)日：2008-01-31
申请号：US11878796
申请日：2007-07-26
IPC分类号： H01L21/311 , H01L21/302 , H01L23/48
CPC分类号： H01L21/3065 , H01L21/30655 , H01L21/31138 , H01L21/76898 , H01L2224/02372 , H01L2224/05008 , H01L2224/05009 , H01L2224/05025 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2224/16 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2924/00014 , H01L2924/04953 , H01L2924/0496 , H01L2924/01074 , H01L2924/0494
摘要： The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus. Then a process of removing the damaged layer on the back surface of the semiconductor substrate and a process of smoothing the sidewall of the via hole are simultaneously performed subsequently after the ashing process in the same apparatus.
摘要翻译： 本发明提供一种制造半导体器件的方法，该方法实现了高可靠性和高产率以及高生产效率。 对半导体基板进行背面研磨（背面研磨）以使半导体基板变薄。 此时不会去除由背面磨削形成的损伤层，并且在半导体衬底的背面上选择性地形成光致抗蚀剂层。 然后使用光致抗蚀剂层作为掩模蚀刻半导体衬底以形成通孔。 然后在形成通孔之后，半导体衬底仍然放置在蚀刻工艺中使用的蚀刻器中，去除光致抗蚀剂层。 以这种方式，在一个装置中顺序地执行蚀刻处理和下一个灰化处理。 然后，在同一装置的灰化处理之后，随后进行去除半导体基板背面的损伤层的工序和平滑通路孔的侧面的工序。
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