公开(公告)号：US20120187562A1

公开(公告)日：2012-07-26

申请号：US13436039

申请日：2012-03-30

Applicant: Takashi Hisada ,  Katsuyuki Yonehara

Inventor： Takashi Hisada ,  Katsuyuki Yonehara

IPC: H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/06136 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/84203 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85191 ,  H01L2224/92247 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract translation: 半导体封装包括布线基板，半导体芯片和导体板，以便减少由设置在芯片周围的外围连接焊盘引起的布线电阻引起的芯片中心部分的电压降。 用于接地/供电的中央电极焊盘设置在芯片的中心部分。 用于接地/供电的导体板设置在芯片上，使得绝缘层位于它们之间。 芯片和导体板上的中心电极焊盘通过形成在绝缘层和导体板中的开口进行引线接合而连接在一起。 导体板的提取部分连接到布线基板上的电源布线焊盘。 优选地，导体板由多层结构构成，并且每个导体板用于电源布线或接地布线。

公开(公告)号：US20110199737A1

公开(公告)日：2011-08-18

申请号：US13097465

申请日：2011-04-29

Applicant: Katsuyuki Yonehara

Inventor： Katsuyuki Yonehara

IPC: H05K7/00

CPC classification number: H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract translation: 本发明的实施例提供一种半导体封装，其包括：连接有多条电线的一端的半导体芯片; 以及其上固定有半导体芯片的板，并且布置有多个相应的导线连接到的多个板布线，其中所述板包括：第一布线对，其包括彼此平行的第一对布线 以及连接到相应导线的前两个电路板线，其中一个电线连接到与另一个电路板电线交叉的一个电路板电线，而不与另一个电路板接线接触;以及第二配线对，其设置成与第一配线对相邻， 包括彼此平行的第二对电线和连接到相应电线而没有交叉的第二两个电路板电线。

公开(公告)号：US5394675A

公开(公告)日：1995-03-07

申请号：US42218

申请日：1993-04-02

Applicant: Katsuyuki Yonehara

Inventor： Katsuyuki Yonehara

IPC: H01L21/60 ,  H01L21/603 ,  H01L23/495 ,  B65B61/14

CPC classification number: H01L23/49572 ,  H01L24/86 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10T29/49121 ,  Y10T29/49144

Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes means for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.

Abstract translation: 公开了一种TAB（胶带自动粘合）带，其包括一个或多个开口，每个开口适于接收半导体芯片，以及延伸到每个这样的开口中的电引线。 重要的是，该TAB带还包括用于防止位于带开口内的半导体芯片由于电引线粘附到接合工具而被朝向接合工具提升的手段，当接合工具用于将接触焊盘接合在 将半导体芯片连接到引线延伸到开口中。

公开(公告)号：US08952551B2

公开(公告)日：2015-02-10

申请号：US13436039

申请日：2012-03-30

Applicant: Takashi Hisada ,  Katsuyuki Yonehara

Inventor： Takashi Hisada ,  Katsuyuki Yonehara

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/06136 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/84203 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85191 ,  H01L2224/92247 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract translation: 半导体封装包括布线基板，半导体芯片和导体板，以便减少由设置在芯片周围的外围连接焊盘引起的布线电阻引起的芯片中心部分的电压降。 用于接地/供电的中央电极焊盘设置在芯片的中心部分。 用于接地/供电的导体板设置在芯片上，使得绝缘层位于它们之间。 芯片和导体板上的中心电极焊盘通过形成在绝缘层和导体板中的开口进行引线接合而连接在一起。 导体板的提取部分连接到布线基板上的电源布线焊盘。 优选地，导体板由多层结构构成，并且每个导体板用于电源布线或接地布线。

公开(公告)号：US08446735B2

公开(公告)日：2013-05-21

申请号：US13097465

申请日：2011-04-29

Applicant: Katsuyuki Yonehara

Inventor： Katsuyuki Yonehara

IPC: H05K7/00

CPC classification number: H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract translation: 本发明的实施例提供一种半导体封装，其包括：连接有多条电线的一端的半导体芯片; 以及其上固定有半导体芯片的板，并且布置有多个相应的导线连接到的多个板布线，其中所述板包括：第一布线对，其包括彼此平行的第一对布线 以及连接到相应导线的前两个电路板线，其中一个电线连接到与另一个电路板电线交叉的一个电路板电线，而不与另一个电路板接线接触;以及第二配线对，其设置成与第一配线对相邻， 包括彼此平行的第二对电线和连接到相应电线而没有交叉的第二两个电路板电线。

公开(公告)号：US20090085155A1

公开(公告)日：2009-04-02

申请号：US11864247

申请日：2007-09-28

Applicant: Mark J. Bailey ,  Todd A. Cannon ,  Haitian Hu ,  Nanju Na ,  Katsuyuki Yonehara ,  Deborah E. Zwitter

Inventor： Mark J. Bailey ,  Todd A. Cannon ,  Haitian Hu ,  Nanju Na ,  Katsuyuki Yonehara ,  Deborah E. Zwitter

IPC: H01L29/00 ,  G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/40 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect.

Abstract translation: 一种用于高速集成电路（IC）的封装对板阻抗匹配的方法。 多个焊球连接到IC封装。 IC封装包括多个导电互连层，其中一个导电互连层耦合到多个焊球中的一个或多个。 多个通孔耦合在不同的导电互连层之间。 电感元件耦合在IC封装内的导电互连层中的互连引线和通孔焊盘之间。 电感元件的物理布局尺寸被配置为使得感应元件提供足以抵消由导电互连层和焊球提供的寄生电容的电感值。 电感元件可以是接合线，电感互连或螺旋互连。

公开(公告)号：US20080237856A1

公开(公告)日：2008-10-02

申请号：US12054156

申请日：2008-03-24

Applicant: Takashi Hisada ,  Katsuyuki Yonehara

Inventor： Takashi Hisada ,  Katsuyuki Yonehara

IPC: H01L23/49 ,  H01L21/60

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/06136 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/84203 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85191 ,  H01L2224/92247 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps. Preferably, the conductor plate is composed of a multilayer structure of two or more layers, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract translation: 半导体封装包括布线基板，半导体芯片和导体板，以便减少由设置在半导体封装中的芯片周围的外围连接焊盘引起的布线电阻引起的芯片中心部分处的电压降 。 用于接地/供电的中央电极焊盘设置在芯片的中心部分。 用于接地/供电的导体板设置在芯片上，使得绝缘层位于它们之间。 芯片和导体板上的中心电极焊盘通过形成在绝缘层和导体板中的开口进行引线接合而连接在一起。 导体板的提取部分连接到布线基板上的电源布线焊盘。 中心电极焊盘和导体板也可以使用金柱凸块连接在一起。 优选地，导体板由两层或多层的多层结构构成，并且每个导体板用于电源布线或接地布线。

公开(公告)号：US5243141A

公开(公告)日：1993-09-07

申请号：US793897

申请日：1991-11-18

Applicant: Katsuyuki Yonehara

Inventor： Katsuyuki Yonehara

IPC: H01L21/60 ,  H01L21/603 ,  H01L23/495

CPC classification number: H01L23/49572 ,  H01L24/86 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10T29/49121 ,  Y10T29/49144

Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes a device for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.