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81 条记录 (耗时 0.036 秒)

    Method of producing a bipolar transistor
    1.
    发明授权
    Method of producing a bipolar transistor 失效
    双极晶体管的制造方法

    公开(公告)号：US5925574A

    公开(公告)日：1999-07-20

    申请号：US865646

    申请日：1992-04-10

    申请人： Kenji Aoki ,  Tadao Akamine ,  Yoshikazu Kojima

    发明人： Kenji Aoki ,  Tadao Akamine ,  Yoshikazu Kojima

    IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/265

    CPC分类号： H01L29/66287 ,  H01L21/2254 ,  Y10S148/017 ,  Y10S148/034 ,  Y10S148/144

    摘要： A method of producing a bipolar transistor composed of collector, base and emitter regions disposed sequentially on a semiconductor substrate. According to the method, a semiconductor layer is deposited on the collector region, the semiconductor layer is cleaned to expose an active surface, an impurity source gas is applied to the exposed active surface while heating the substrate to form an impurity adsorption layer, the impurity is diffused into the semiconductor layer to form the base region, another semiconductor layer is deposited on the base region, this semiconductor layer is cleaned to expose an active surface, another impurity source gas is applied to the exposed active surface while heating the substrate to form another impurity adsorption layer, and impurity is diffused into the semiconductor layer to from the impurity adsorption layer to form the emitter region.

    摘要翻译： 一种制造由依次设置在半导体衬底上的集电极，基极和发射极组成的双极晶体管的方法。 根据该方法，在集电极区域上淀积半导体层，对半导体层进行清洗以露出活性表面，在对基板进行加热而形成杂质吸附层的同时，向露出的活性表面施加杂质源气体，杂质吸附层 扩散到半导体层中以形成基极区域，另一半导体层沉积在基极区上，该半导体层被清洁以暴露活性表面，另一杂质源气体被加到暴露的有源表面上，同时加热衬底形成 另一杂质吸附层，杂质从杂质吸附层扩散到半导体层中，形成发射极区域。

    Impurity doping method with diffusion source of boron-silicide film
    3.
    发明授权
    Impurity doping method with diffusion source of boron-silicide film 失效
    掺杂掺杂硼硅化物膜扩散源的方法

    公开(公告)号：US5753530A

    公开(公告)日：1998-05-19

    申请号：US449655

    申请日：1995-05-24

    申请人： Tadao Akamine ,  Naoto Saito ,  Kenji Aoki ,  Yoshikazu Kojima

    发明人： Tadao Akamine ,  Naoto Saito ,  Kenji Aoki ,  Yoshikazu Kojima

    IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/306 ,  H01L21/331 ,  H01L21/336 ,  H01L21/385

    CPC分类号： H01L21/02046 ,  H01L21/2257 ,  H01L21/28512 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66575 ,  Y10S438/906

    摘要： A solid phase diffusion process using boron silicide film as diffusion source to improve controllability of diffusion of boron impurity into a silicon substrate in order to achieve a shallow junction. The process includes: cleaning the surface of a Si substrate by removing the native oxide film thereof to expose an active surface; treating the active surface to form thereon a boron silicide film as an impurity source; and introducing boron impurity from the boron silicide film into the Si substrate to form a boron diffusion layer. In this manner, a boron diffusion layer having a high surface concentration and a shallow junction can be formed because the boron silicide film is formed directly on the surface of the Si substrate. Because the boron silicide film is chemically and physically stable, an improved diffusion controllability is obtained. The diffusion controllability is further improved by accurately evaluating the impurity film optically during the fabrication process. A structure composed of a boron diffusion layer and a boron silicide region provides a high speed, highly integrated, and highly reliable semiconductor device, particularly when the boron silicide region is disposed between an impurity region and an electrode metal.

    摘要翻译： 使用硅化硅膜作为扩散源的固相扩散工艺，以提高硼杂质扩散到硅衬底中的可控性，以便实现浅结。 该方法包括：通过去除其自然氧化膜以暴露活性表面来清洁Si衬底的表面; 处理活性表面以形成作为杂质源的硼化硅膜; 并将硼杂质从硅化硅膜引入Si衬底中以形成硼扩散层。 以这种方式，可以形成具有高表面浓度和浅结的硼扩散层，因为硅化硅膜直接形成在Si衬底的表面上。 因为硼化硅膜在化学和物理上是稳定的，所以获得改进的扩散控制性。 通过在制造过程中光学地精确评估杂质膜，进一步提高了扩散控制性。 由硼扩散层和硼硅化物区组成的结构提供高速，高度集成且高度可靠的半导体器件，特别是当硅化硼区域设置在杂质区域和电极金属之间时。

    Low power oscillation circuit and non-volatile semiconductor memory having ring oscillator
    5.
    发明授权
    Low power oscillation circuit and non-volatile semiconductor memory having ring oscillator 失效
    低功耗振荡电路和具有环形振荡器的非易失性半导体存储器

    公开(公告)号：US06188293B1

    公开(公告)日：2001-02-13

    申请号：US08713089

    申请日：1996-09-16

    申请人： Masanori Miyagi ,  Yoshikazu Kojima

    发明人： Masanori Miyagi ,  Yoshikazu Kojima

    IPC分类号： H03B524

    CPC分类号： H03K3/011 ,  H03K3/0315 ,  H03K3/354 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03K2005/00195

    摘要： An low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change includes a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.

    摘要翻译： 能够在宽电压范围内稳定工作而不经历大的频率变化的低功耗集成环形振荡器包括具有增强型P-MOS晶体管和耗尽型N-MOS晶体管的第一恒定电压产生电路和第二常数 具有耗尽型N-MOS晶体管和增强型N-MOS晶体管的电压产生电路。 由第一恒压电路产生的第一恒定电压被施加到连接在环形振荡器的各个级联反相器之间的传输门的P-MOS晶体管的栅电极。 由第二恒压产生电路产生的第二恒定电压连接到传输门的N-MOS晶体管的栅电极。 通过这种结构，电流消耗降低，并且可以提高电池寿命。 用于写入和擦除EEPROM电路的升压电路可以由低功率环形振荡器形成。

    Charge/discharge control circuit and chargeable electric power source apparatus
    7.
    发明授权
    Charge/discharge control circuit and chargeable electric power source apparatus 有权
    充放电控制电路和充电电源装置

    公开(公告)号：US6097177A

    公开(公告)日：2000-08-01

    申请号：US196699

    申请日：1998-11-20

    申请人： Minoru Sudo ,  Takayuki Takashina ,  Yoshikazu Kojima ,  Sadashi Shimoda ,  Hiroshi Mukainakano

    发明人： Minoru Sudo ,  Takayuki Takashina ,  Yoshikazu Kojima ,  Sadashi Shimoda ,  Hiroshi Mukainakano

    IPC分类号： H02J7/00 ,  H02J7/14 ,  H01M10/46

    CPC分类号： H02J7/0026 ,  H02J7/0031 ,  H02J7/1438 ,  H02J2007/004 ,  H02J7/0034

    摘要： A charge/discharge control circuit for controlling the charging and discharging of a secondary cell has a voltage dividing circuit for dividing an output voltage of the secondary cell, which may comprise plural cells, an overcharge detection circuit for detecting an overcharge state of the secondary cell, an overdischarge detection circuit for detecting an overdischarge state of the secondary cell, and a control circuit for receiving and processing an output signal of the overcharge detecting circuit and the overdischarge detecting circuit and controlling the switch. In a preferred embodiment, an overcharge reference voltage source used for the overcharge voltage detection circuit is used also as an overdischarge reference voltage source for the overdischarge voltage detection circuit.

    摘要翻译： 用于控制二次电池的充电和放电的充电/放电控制电路具有分压电路，用于对可能包括多个电池的二次电池的输出电压进行分压，用于检测二次电池的过充电状态的过充电检测电路 用于检测二次电池的过放电状态的过放电检测电路，以及用于接收和处理过充电检测电路和过放电检测电路的输出信号并控制开关的控制电路。 在优选实施例中，用于过充电电压检测电路的过充电参考电压源也用作过放电电压检测电路的过放电参考电压源。

    High voltage inverter circuit
    8.
    发明授权
    High voltage inverter circuit 失效
    高压逆变电路

    公开(公告)号：US5965921A

    公开(公告)日：1999-10-12

    申请号：US680346

    申请日：1996-07-17

    申请人： Yoshikazu Kojima

    发明人： Yoshikazu Kojima

    IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76 ,  H01L27/01 ,  H01L29/00 ,  H01L29/94

    CPC分类号： H01L27/0688 ,  H01L27/0922

    摘要： In an integrated circuit type semiconductor device consisting of MISFETs, high rated voltage characteristic is obtained in a gate insulation film structure of a thin film. Further, a reduction in the manufacturing cost of semiconductor devices including high-rated voltage and low rated voltage MISFETs. An intermediate gate electrode is provided which overlies a channel formation region and a gate region with the same gate insulation film being sandwiched therebetween. The gate region is provided on the surface of a substrate. The channel formation region has an impedance indirectly controllable via the intermediate gate electrode upon application of a voltage to the gate region. The intermediate gate electrode is provided with a voltage reset(set) means connected thereto for eliminating the occurrence of charge-up.

    摘要翻译： 在由MISFET组成的集成电路型半导体器件中，在薄膜的栅绝缘膜结构中获得高额定电压特性。 此外，降低包括高额定电压和低额定电压MISFET的半导体器件的制造成本。 提供了一个中间栅极电极，其位于沟道形成区域和栅极区域之间，其间夹有相同的栅极绝缘膜。 栅极区域设置在基板的表面上。 沟道形成区域在向栅极区域施加电压时具有经由中间栅电极间接控制的阻抗。 中间栅电极设置有与其连接的电压复位（集合）装置，以消除充电的发生。