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    Small geometry high voltage semiconductor device
    2.
    发明授权
    Small geometry high voltage semiconductor device 失效
    小几何高压半导体器件

    公开(公告)号：US06222235B1

    公开(公告)日：2001-04-24

    申请号：US08677541

    申请日：1996-07-10

    申请人： Yoshikazu Kojima ,  Kazutoshi Ishii ,  Masaaki Kamiya ,  Yasuhiro Moya

    发明人： Yoshikazu Kojima ,  Kazutoshi Ishii ,  Masaaki Kamiya ,  Yasuhiro Moya

    IPC分类号： H01L2362

    CPC分类号： H01L29/7834 ,  H01L27/0266 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

    摘要翻译： 在其输出部分中包括多个高电压驱动晶体管的半导体器件通过将静电保护晶体管与连接到输出焊盘的高电压驱动晶体管并联连接来提高静电耐受电压。 使静电保护晶体管的漏极耐受电压低于高电压驱动晶体管的漏极耐受电压。 此外，静电保护晶体管的沟道长度变短，以实现静电保护晶体管的高效双极性操作。

    Current regulating semiconductor integrated circuit device and fabrication method of the same
    7.
    发明授权
    Current regulating semiconductor integrated circuit device and fabrication method of the same 失效
    电流调节半导体集成电路器件及其制造方法

    公开(公告)号：US5663589A

    公开(公告)日：1997-09-02

    申请号：US314140

    申请日：1994-09-28

    申请人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

    发明人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

    IPC分类号： H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/76 ,  H01L21/04

    CPC分类号： H01L27/0814 ,  Y10S257/907 ,  Y10S257/91

    摘要： A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

    摘要翻译： 具有电流调节二极管的半导体集成器件可以通过形成多个MOS晶体管的电流调节二极管来大大减小尺寸并提高其性能，每个MOS晶体管具有形成在半导体衬底中的栅极，漏极区域和源极区域， 源极区域和衬底区域彼此电耦合，至少两个MOS晶体管的漏极区域电耦合，并且每个MOS晶体管的源极区域电耦合，耦合的漏极区域，耦合的 源极区域和耦合栅极分别形成漏极端子，源极端子和栅极端子。 为了设定期望的调节电流，可以切断电流调节二极管中的选择的耦合线。 这可以例如通过测量在漏极端子中流动的第一电流，同时向栅极端子施加第一电压，并且相对于源极端子的电位向漏极端子施加第二电压，然后测量第二电压 相对于源极端子的电位向漏极端子施加第三电压而向漏极端子施加第三电压而流过漏极端子的电流。 为了实现期望的电流特性，然后切割耦合的漏极之间或耦合的源之间的选定的导线。

    Method of producing low and high voltage MOSFETs with reduced masking steps
    8.
    发明授权
    Method of producing low and high voltage MOSFETs with reduced masking steps 失效
    降低屏蔽步骤生产低压和高压MOSFET的方法

    公开(公告)号：US5449637A

    公开(公告)日：1995-09-12

    申请号：US128059

    申请日：1993-09-27

    申请人： Yutaka Saito ,  Yoshikazu Kojima ,  Kazutoshi Ishii

    发明人： Yutaka Saito ,  Yoshikazu Kojima ,  Kazutoshi Ishii

    IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/8238

    摘要： An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device. The impurity can be doped by ion implantation while covering the film 100 with the photoresist, thereby facilitating micronization and integration of the semiconductor device.

    摘要翻译： 在半导体衬底1的表面上形成导电或绝缘膜100.第一光致抗蚀剂101涂覆在膜100上，然后被图案化。 通过蚀刻选择性地去除膜100以暴露衬底1的给定区域。随后将第一导电类型的杂质掺杂到暴露区域中以形成第一杂质区域。 在去除第一光致抗蚀剂101之后，将第二光致抗蚀剂103整个涂覆在膜100上，然后被图案化。 随后，通过蚀刻从另一给定区域选择性地去除膜100。 第二导电类型的另一杂质被掺杂到暴露区域中以形成第二杂质区域104.只进行光致抗蚀剂图案化的两个步骤以形成不同导电类型的杂质区域，从而降低半导体的制造成本 设备。 可以通过离子注入来掺杂杂质，同时用光致抗蚀剂覆盖膜100，从而有助于半导体器件的微粉化和集成。

    Method of manufacturing a semiconductor chip
    10.
    发明授权
    Method of manufacturing a semiconductor chip 失效
    制造半导体芯片的方法

    公开(公告)号：US6107163A

    公开(公告)日：2000-08-22

    申请号：US81987

    申请日：1998-05-20

    申请人： Yoshikazu Kojima ,  Masaaki Kamiya

    发明人： Yoshikazu Kojima ,  Masaaki Kamiya

    IPC分类号： H01L21/301 ,  B23D57/00 ,  B28D5/04 ,  H01L21/304 ,  H01L21/46

    CPC分类号： H01L21/3043 ,  B23D57/0023 ,  B28D5/045

    摘要： In a method of manufacturing a semiconductor chip, a wire is traveled in one way to cut a wafer into a plurality of chips while a wire train where wires are arranged by pitches of scribe lines is brought into contact with the scribe lines of the wafer linearly, and an abrasive solution is supplied to a contact portion thereof.

    摘要翻译： 在制造半导体芯片的方法中，将导线以一种方式移动以将晶片切割成多个芯片，同时通过划线的间距布置导线的线串与晶片的划线线性地接触 并且将磨料溶液供应到其接触部分。