公开(公告)号：US20100325387A1

公开(公告)日：2010-12-23

申请号：US12787013

申请日：2010-05-25

申请人： Kenji YAMANE ,  Tsuyoshi Kano ,  Masahiro Takahashi

发明人： Kenji YAMANE ,  Tsuyoshi Kano ,  Masahiro Takahashi

IPC分类号： G06F9/302 ,  G06F15/76 ,  G06F9/06

CPC分类号： G06F9/5083

摘要： An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored.

摘要翻译： 运算处理装置包括：多个处理单元，其彼此串联连接，其中每个处理单元包括限制信息设置部分，其中指示每个处理单元的算术处理量为 设置每个算术处理单元的数据处理; 算术部，根据所述限制信息设定部中设定的限制信息，通过所述多个处理部之间的相同程序，对各运算处理部的数据进行运算处理; 以及存储器，其中存储经过运算部分进行运算处理的处理数据。

公开(公告)号：US08601238B2

公开(公告)日：2013-12-03

申请号：US12787013

申请日：2010-05-25

申请人： Kenji Yamane ,  Tsuyoshi Kano ,  Masahiro Takahashi

发明人： Kenji Yamane ,  Tsuyoshi Kano ,  Masahiro Takahashi

IPC分类号： G06F9/00

CPC分类号： G06F9/5083

摘要： An arithmetic processing apparatus includes: a plurality of processing units connected in series to each other, wherein each of the processing units includes a limitation information setting section in which limitation information, which indicates the amount of arithmetic processing that each of the processing units is to process for data of each arithmetic processing unit, is set; an arithmetic section which executes arithmetic processing on the data of each arithmetic processing unit, according to the limitation information set in the limitation information setting section, by the same program between the plurality of processing units; and a memory in which processing data subjected to the arithmetic processing by the arithmetic section is stored.

摘要翻译： 运算处理装置包括：多个处理单元，其彼此串联连接，其中每个处理单元包括限制信息设置部分，其中指示每个处理单元的算术处理量为 设置每个算术处理单元的数据处理; 算术部，根据所述限制信息设定部中设定的限制信息，通过所述多个处理部之间的相同程序，对各运算处理部的数据进行运算处理; 以及存储器，其中存储经过运算部分进行运算处理的处理数据。

公开(公告)号：US20130070970A1

公开(公告)日：2013-03-21

申请号：US13610442

申请日：2012-09-11

申请人： Kenji Yamane ,  Masahiro Takahashi ,  Shinji Watanabe ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Hiroshi Kyusojin

发明人： Kenji Yamane ,  Masahiro Takahashi ,  Shinji Watanabe ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Hiroshi Kyusojin

IPC分类号： G06T7/00

CPC分类号： G02B21/367 ,  G02B21/0004 ,  G06T7/0012

摘要： An information processing apparatus includes a memory and a control unit. The memory stores a first image. The control unit divides the first image into a plurality of regions. Further, the control unit calculates a likelihood of an existence of a sample in the plurality of regions thus divided for each of the plurality of regions. Further, the control unit generates an existence map based on the calculated likelihood, the existence map having the plurality of regions classified into first regions, second regions, and third regions. Further, the control unit generates imaging sequence information based on the generated existence map, the imaging sequence information indicating imaging sequences such that the first regions are imaged prior to the second regions and a total movement distance of a stage for imaging the first and second regions becomes minimum.

摘要翻译： 信息处理装置包括存储器和控制单元。 存储器存储第一图像。 控制单元将第一图像划分成多个区域。 此外，控制单元计算对于多个区域中的每一个而对这样划分的多个区域中的样本的存在的可能性。 此外，控制单元基于计算出的可能性生成存在图，该存在图具有分为第一区域，第二区域和第三区域的多个区域。 此外，控制单元基于生成的存在图来生成成像序列信息，指示成像序列的成像序列信息，使得第一区域在第二区域之前被成像，以及用于对第一和第二区域进行成像的载物台的总移动距离 变得最小。

公开(公告)号：US08934699B2

公开(公告)日：2015-01-13

申请号：US13610442

申请日：2012-09-11

申请人： Kenji Yamane ,  Masahiro Takahashi ,  Shinji Watanabe ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Hiroshi Kyusojin

发明人： Kenji Yamane ,  Masahiro Takahashi ,  Shinji Watanabe ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Hiroshi Kyusojin

IPC分类号： G06K9/00 ,  G02B21/36 ,  G06T7/00 ,  G02B21/00

CPC分类号： G02B21/367 ,  G02B21/0004 ,  G06T7/0012

摘要： An information processing apparatus includes a memory and a control unit. The memory stores a first image. The control unit divides the first image into a plurality of regions. Further, the control unit calculates a likelihood of an existence of a sample in the plurality of regions thus divided for each of the plurality of regions. Further, the control unit generates an existence map based on the calculated likelihood, the existence map having the plurality of regions classified into first regions, second regions, and third regions. Further, the control unit generates imaging sequence information based on the generated existence map, the imaging sequence information indicating imaging sequences such that the first regions are imaged prior to the second regions and a total movement distance of a stage for imaging the first and second regions becomes minimum.

摘要翻译： 信息处理装置包括存储器和控制单元。 存储器存储第一图像。 控制单元将第一图像划分成多个区域。 此外，控制单元计算对于多个区域中的每一个而对这样划分的多个区域中的样本的存在的可能性。 此外，控制单元基于计算出的可能性生成存在图，该存在图具有分为第一区域，第二区域和第三区域的多个区域。 此外，控制单元基于生成的存在图来生成成像序列信息，指示成像序列的成像序列信息，使得第一区域在第二区域之前被成像，以及用于对第一和第二区域进行成像的载物台的总移动距离 变得最小。

公开(公告)号：US09911856B2

公开(公告)日：2018-03-06

申请号：US12900145

申请日：2010-10-07

申请人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Junichiro Sakata

发明人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Junichiro Sakata

IPC分类号： H01L29/786 ,  H01L29/423

CPC分类号： H01L29/7869 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/78696

摘要： One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

公开(公告)号：US09635313B2

公开(公告)日：2017-04-25

申请号：US13538560

申请日：2012-06-29

申请人： Yutaka Hasegawa ,  Yoichi Mizutani ,  Masato Kajimoto ,  Masahiro Takahashi ,  Hiroshi Kyusojin

发明人： Yutaka Hasegawa ,  Yoichi Mizutani ,  Masato Kajimoto ,  Masahiro Takahashi ,  Hiroshi Kyusojin

IPC分类号： H04N7/15 ,  G06F3/0484 ,  H04L12/18 ,  G06Q10/10 ,  H04L29/06 ,  G06F17/30

CPC分类号： G06F3/04845 ,  G06F3/1454 ,  G06F17/30056 ,  G06F2203/04803 ,  G06F2203/04806 ,  G06Q10/10 ,  H04L12/1813 ,  H04L12/1822 ,  H04L12/1827 ,  H04L65/403 ,  H04M2250/62 ,  H04N7/15

摘要： An information processing system and a method for operating same are provided. The information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus is configured to display a first synchronous image in a first window, the first window having an operation right. The second information processing apparatus has a synchronous state or an asynchronous state. The second information processing apparatus is configured to: display a second synchronous image; in response to a first request, switch from the synchronous state to the asynchronous state; and in response to a second request, switch from the asynchronous state to the synchronous state.

公开(公告)号：US09627198B2

公开(公告)日：2017-04-18

申请号：US12894791

申请日：2010-09-30

申请人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Junichiro Sakata

发明人： Shunpei Yamazaki ,  Akiharu Miyanaga ,  Masahiro Takahashi ,  Hideyuki Kishida ,  Junichiro Sakata

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L21/02554 ,  G02F1/1368 ,  G02F1/167 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02266 ,  H01L21/02422 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.

公开(公告)号：US09535834B2

公开(公告)日：2017-01-03

申请号：US14563645

申请日：2014-12-08

申请人： Dong-Keun Kim ,  Masahiro Takahashi ,  Tsuneo Inaba

发明人： Dong-Keun Kim ,  Masahiro Takahashi ,  Tsuneo Inaba

IPC分类号： G06F12/08 ,  G11C13/00 ,  G11C11/4099 ,  G11C11/16

CPC分类号： G11C13/004 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0207 ,  G06F12/08 ,  G06F12/0875 ,  G06F2212/2024 ,  G06F2212/452 ,  G06F2212/60 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4099 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2213/79 ,  G11C2213/82

摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.

摘要翻译： 电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压 阵列 第一读取控制单元; 和第二读取控制单元。

公开(公告)号：US09484091B2

公开(公告)日：2016-11-01

申请号：US14636740

申请日：2015-03-03

申请人： Masahiro Takahashi ,  Akira Katayama ,  Dong Keun Kim ,  Byoung Chan Oh

发明人： Masahiro Takahashi ,  Akira Katayama ,  Dong Keun Kim ,  Byoung Chan Oh

IPC分类号： G11C11/16 ,  G11C13/00

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/00 ,  G11C13/0026 ,  G11C13/0061 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/79

摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

公开(公告)号：US09398233B2

公开(公告)日：2016-07-19

申请号：US13880267

申请日：2012-07-10

申请人： Hiroshi Kyusojin ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Masahiro Takahashi

发明人： Hiroshi Kyusojin ,  Yoichi Mizutani ,  Yutaka Hasegawa ,  Masahiro Takahashi

IPC分类号： G06K9/00 ,  H04N5/265 ,  H04N7/15 ,  H04M3/56 ,  G06F19/00 ,  H04L12/18

CPC分类号： H04N5/265 ,  G06F19/00 ,  G06F19/321 ,  G16H80/00 ,  H04L12/1827 ,  H04M3/567 ,  H04N7/15

摘要： An information processing apparatus, an information processing system, and a method of processing information are provided. In one embodiment, the information processing apparatus includes a processor, and a memory device storing instructions. When executed by the processor, the instructions cause the processor to receive, from a first information processing apparatus, area specifying information and location information, the area specifying information specifying a display area in an image, the display area including a plurality of partial images, the location information indicating at least one location of the plurality of partial images. The instructions further cause the processor to transmit, to a second information processing apparatus, the area specifying information and the location information.

摘要翻译： 提供信息处理装置，信息处理系统和处理信息的方法。 在一个实施例中，信息处理设备包括处理器和存储指令的存储器件。 当处理器执行时，指令使得处理器从第一信息处理设备接收区域指定信息和位置信息，区域指定信息指定图像中的显示区域，显示区域包括多个部分图像， 所述位置信息指示所述多个部分图像中的至少一个位置。 所述指令还使所述处理器向所述第二信息处理设备发送所述区域指定信息和所述位置信息。