公开(公告)号：US08890289B2

公开(公告)日：2014-11-18

申请号：US13358133

申请日：2012-01-25

申请人： Kenzo Manabe ,  Naoya Inoue ,  Kenichiro Hijioka ,  Yoshihiro Hayashi

发明人： Kenzo Manabe ,  Naoya Inoue ,  Kenichiro Hijioka ,  Yoshihiro Hayashi

IPC分类号： H01L29/02 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L23/532

CPC分类号： H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

摘要翻译： 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US20110284991A1

公开(公告)日：2011-11-24

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US07750413B2

公开(公告)日：2010-07-06

申请号：US10561089

申请日：2004-06-16

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

IPC分类号： H01L29/76

CPC分类号： H01L28/10 ,  H01L21/8221 ,  H01L23/5227 ,  H01L23/552 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/08 ,  H01L29/0657 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/80001

摘要： An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip.MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.

摘要翻译： 本发明的目的是将包括其中形成的电感器的RF电路和数字电路安装在单个芯片上。 在由元件隔离膜2隔离的区域中的半导体衬底1上形成MOSFET。多个低介电常数绝缘棒包括嵌入其中的低介电常数绝缘体，并穿透第一层间电介质膜4以到达硅衬底的内部 设置在RF电路区域100中。电感器40通过使用多层互连在RF电路区域中的层间电介质膜上形成。 在电感器的芯部及其周围的区域中形成有高导磁率隔离区域，其中包括高导磁率材料和低电容率材料的混合物的复合材料。

公开(公告)号：US20060157798A1

公开(公告)日：2006-07-20

申请号：US10561089

申请日：2004-06-16

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kenichiro Hijioka

IPC分类号： H01L29/76

CPC分类号： H01L28/10 ,  H01L21/8221 ,  H01L23/5227 ,  H01L23/552 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/08 ,  H01L29/0657 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/80001

摘要： [Object] An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip. [Means for Solving Problems] MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.

摘要翻译： 本发明的目的是将包括其中形成的电感器和数字电路的RF电路安装在单个芯片上。 解决问题的手段在由元件隔离膜2隔离的区域中，在半导体基板1上形成MOSFET。 在RF电路区域100中设置有多个低介电常数绝缘棒，其包括嵌入其中的低介电常数绝缘体并且穿透第一层间电介质膜4以到达硅衬底的内部。 通过使用多层互连，在RF电路区域中的层间电介质膜上形成电感器40。 在电感器的芯部及其周围的区域中形成有高导磁率隔离区域，其中包括高导磁率材料和低电容率材料的混合物的复合材料。

公开(公告)号：US20130056850A1

公开(公告)日：2013-03-07

申请号：US13593084

申请日：2012-08-23

申请人： Ippei KUME ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

发明人： Ippei KUME ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

IPC分类号： H01L27/04 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/90

摘要： To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

摘要翻译： 提供具有降低的电容特性变化的半导体器件。 在半导体装置中，在凹部（孔）的上端部的周围设有保护层。 该保护层的介电常数高于与保护层位于同一层的绝缘层的介电常数，并且构成放置在逻辑电路区域中的多层布线层。

公开(公告)号：US08946800B2

公开(公告)日：2015-02-03

申请号：US13593084

申请日：2012-08-23

申请人： Ippei Kume ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

发明人： Ippei Kume ,  Kenichiro Hijioka ,  Naoya Inoue ,  Hiroyuki Kunishima ,  Manabu Iguchi ,  Hiroki Shirai

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10894 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/90

摘要： To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

摘要翻译： 提供具有降低的电容特性变化的半导体器件。 在半导体装置中，在凹部（孔）的上端部的周围设有保护层。 该保护层的介电常数高于与保护层位于同一层的绝缘层的介电常数，并且构成放置在逻辑电路区域中的多层布线层。

公开(公告)号：US08558334B2

公开(公告)日：2013-10-15

申请号：US13399475

申请日：2012-02-17

申请人： Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/82 ,  H01L23/552 ,  H01L27/08 ,  H01L21/00

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

摘要翻译： 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US08378341B2

公开(公告)日：2013-02-19

申请号：US12654205

申请日：2009-12-14

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC分类号： H01L29/18 ,  H01L21/00

CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

摘要翻译： 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US06300212B1

公开(公告)日：2001-10-09

申请号：US09124067

申请日：1998-07-29

申请人： Naoya Inoue ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L2120

CPC分类号： C23C14/088 ,  H01L21/31691 ,  H01L28/55

摘要： In a method and an apparatus for manufacturing a semiconductor device which has a capacitor consisting of a layered structure of a lower electrode, a ferroelectric layer made of a composite metal oxide such as PZT and an upper electrode in a predetermined region on a semiconductor substrate, the lower electrode, the ferroelectric layer and the upper electrode are successively formed in an atmosphere isolated from the air. For the duration after forming the ferroelectric layer till starting the formation of the upper electrode, it is desirable to introduce a gas such as an inert gas or an inert gas with oxygen into the atmosphere in the vicinity of the substrate to keep the atmosphere within a predetermined pressure range.

摘要翻译： 在半导体装置的制造方法和装置中，具有由下电极构成的电容器，由复合金属氧化物如PZT制成的铁电层和半导体基板上的预定区域中的上电极， 下部电极，铁电层和上部电极依次形成在与空气隔离的气氛中。 在形成铁电层直到开始形成上电极的持续时间之后，期望将惰性气体或惰性气体的气体与氧气引入到基板附近的气氛中，以将气氛保持在 预定压力范围。