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公开(公告)号：US08890289B2
公开(公告)日：2014-11-18
申请号：US13358133
申请日：2012-01-25
IPC分类号： H01L29/02 , H01L21/02 , H01L27/108 , H01L49/02 , H01L23/532
CPC分类号： H01L27/1085 , H01L21/768 , H01L23/5223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L27/10814 , H01L27/10852 , H01L27/10885 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.
摘要翻译： 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。
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公开(公告)号：US08648441B2
公开(公告)日：2014-02-11
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。
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公开(公告)号：US20110284991A1
公开(公告)日：2011-11-24
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro HIJIOKA , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。
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公开(公告)号：US07750413B2
公开(公告)日：2010-07-06
申请号：US10561089
申请日：2004-06-16
IPC分类号： H01L29/76
CPC分类号： H01L28/10 , H01L21/8221 , H01L23/5227 , H01L23/552 , H01L27/0617 , H01L27/0688 , H01L27/08 , H01L29/0657 , H01L2924/00011 , H01L2924/0002 , H01L2924/00 , H01L2224/80001
摘要： An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip.MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.
摘要翻译： 本发明的目的是将包括其中形成的电感器的RF电路和数字电路安装在单个芯片上。 在由元件隔离膜2隔离的区域中的半导体衬底1上形成MOSFET。多个低介电常数绝缘棒包括嵌入其中的低介电常数绝缘体，并穿透第一层间电介质膜4以到达硅衬底的内部 设置在RF电路区域100中。电感器40通过使用多层互连在RF电路区域中的层间电介质膜上形成。 在电感器的芯部及其周围的区域中形成有高导磁率隔离区域，其中包括高导磁率材料和低电容率材料的混合物的复合材料。
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公开(公告)号：US20060157798A1
公开(公告)日：2006-07-20
申请号：US10561089
申请日：2004-06-16
IPC分类号： H01L29/76
CPC分类号： H01L28/10 , H01L21/8221 , H01L23/5227 , H01L23/552 , H01L27/0617 , H01L27/0688 , H01L27/08 , H01L29/0657 , H01L2924/00011 , H01L2924/0002 , H01L2924/00 , H01L2224/80001
摘要： [Object] An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip. [Means for Solving Problems] MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.
摘要翻译： 本发明的目的是将包括其中形成的电感器和数字电路的RF电路安装在单个芯片上。 解决问题的手段在由元件隔离膜2隔离的区域中，在半导体基板1上形成MOSFET。 在RF电路区域100中设置有多个低介电常数绝缘棒，其包括嵌入其中的低介电常数绝缘体并且穿透第一层间电介质膜4以到达硅衬底的内部。 通过使用多层互连，在RF电路区域中的层间电介质膜上形成电感器40。 在电感器的芯部及其周围的区域中形成有高导磁率隔离区域，其中包括高导磁率材料和低电容率材料的混合物的复合材料。
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公开(公告)号：US09042117B2
公开(公告)日：2015-05-26
申请号：US13064036
申请日：2011-03-02
IPC分类号： H05K1/11 , H05K1/14 , H01L23/522
CPC分类号： H01L23/5227 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.
摘要翻译： 半导体器件有效地抑制了电感器元件和位于同一芯片上形成的电感器元件上方的电线之间发生相互作用的问题。 半导体器件包括半导体衬底和覆盖该半导体衬底的多层布线层，多层布线层包括：电感器元件和三个连续的布线和形成在电感器元件上方的第四布线; 和两个固定电压电位的屏蔽导体，从平面图可以看到电感器元件，并形成在电感器元件和三个连续的导线之间，并形成在电感器元件上方的第四根导线。
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7.发明授权Inductor element, inductor element manufacturing method, and semiconductor device with inductor element mounted thereon 有权电感元件，电感器元件制造方法以及安装有电感器元件的半导体器件公开(公告)号：US08339230B2
公开(公告)日：2012-12-25
申请号：US12375944
申请日：2007-08-01
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/34 , H01F41/041 , H01F2017/002 , H01F2017/004 , H01F2017/0086 , Y10T29/4902 , Y10T29/49071
摘要： An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.
摘要翻译： 电感器元件形成在多层引线结构中，该多层引线结构包括引线，绝缘层和绝缘层，绝缘层和设置在绝缘层中的通孔以及连接引线上和下的引线层是多层叠层，其特征在于： 至少一对垂直相邻引线的至少一部分是线圈引线; 线圈引线串联连接，其中垂直相邻的线圈引线的电流方向通过设置在其端部上的通孔相同，并形成串联电感; 并且垂直相邻的线圈引线的引线间电容大于形成在同一引线层中的其它线圈引线之间的引线间电容。
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公开(公告)号：US20110235302A1
公开(公告)日：2011-09-29
申请号：US13064036
申请日：2011-03-02
IPC分类号： H05K7/02
CPC分类号： H01L23/5227 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method to effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.
摘要翻译： 一种半导体器件和制造方法，用于有效地抑制电感器元件和位于同一芯片上形成的电感器元件上方的电线之间发生相互作用的问题。 半导体器件包括半导体衬底和覆盖该半导体衬底的多层布线层，多层布线层包括：电感器元件和三个连续的布线和形成在电感器元件上方的第四布线; 和两个固定电压电位的屏蔽导体，从平面图可以看到电感器元件，并形成在电感器元件和三个连续的导线之间，并形成在电感器元件上方的第四根导线。
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9.发明授权Porous insulating film, method for producing the same, and semiconductor device using the same 有权多孔绝缘膜及其制造方法以及使用其的半导体装置公开(公告)号：US07968471B2
公开(公告)日：2011-06-28
申请号：US10580606
申请日：2004-11-29
IPC分类号： H01L21/31
CPC分类号： H01L21/02126 , C23C16/401 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31695 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating film. Gas containing molecule vapor of at least one or more organic silica compounds, which have a cyclic silica skeleton in its molecule and have at least one or more unsaturated hydrocarbon groups bound with the cyclic silica skeleton is introduced into plasma to grow a porous insulating film on a semiconductor substrate.
摘要翻译： 本发明提供一种制造作为构成半导体器件的绝缘膜有效的多孔绝缘膜的方法以及与半导体材料具有高粘合性的多孔绝缘膜的制造方法，所述半导体材料与所述半导体材料的上下界面接触 绝缘膜。 在其分子中具有环状二氧化硅骨架并且具有与环状二氧化硅骨架结合的至少一个以上不饱和烃基的至少一种以上有机二氧化硅化合物的含有气体的分子蒸气被引入等离子体中以在多孔绝缘膜上生长多孔绝缘膜 半导体衬底。
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10.发明申请INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON 有权电感器元件，电感器元件制造方法和具有电感元件的半导体器件安装在其上公开(公告)号：US20090315662A1
公开(公告)日：2009-12-24
申请号：US12375944
申请日：2007-08-01
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/34 , H01F41/041 , H01F2017/002 , H01F2017/004 , H01F2017/0086 , Y10T29/4902 , Y10T29/49071
摘要： An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.
摘要翻译： 电感器元件形成在多层引线结构中，该多层引线结构包括引线，绝缘层和绝缘层，绝缘层和设置在绝缘层中的通孔以及连接引线上和下的引线层是多层叠层，其特征在于： 至少一对垂直相邻引线的至少一部分是线圈引线; 线圈引线串联连接，其中垂直相邻的线圈引线的电流方向通过设置在其端部上的通孔相同，并形成串联电感; 并且垂直相邻的线圈引线的引线间电容大于形成在同一引线层中的其它线圈引线之间的引线间电容。
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