公开(公告)号：US20090000942A1

公开(公告)日：2009-01-01

申请号：US12145850

申请日：2008-06-25

申请人： Keun-Hee Bai ,  Yoon-Jae Kim ,  Yong-Jin Kim

发明人： Keun-Hee Bai ,  Yoon-Jae Kim ,  Yong-Jin Kim

IPC分类号： B01J19/08 ,  C23C14/34 ,  C23F1/08

CPC分类号： H05H1/46 ,  H01J37/32082 ,  H01J37/32183

摘要： A pulse plasma matching system includes an RF matching box configured to receive an RF power pulse generated by an RF power source, configured to perform a plasma impedance matching, and configured to apply the RF power pulse to a process chamber, and a network analyzer configured to measure an impedance of plasma generated in a process chamber. A controller is configured to generate a capacitance control signal corresponding to a plasma impedance value measured by the network analyzer, configured to supply the capacitance control signal to the RF matching box, and configured to generate an impedance matching compensation pulse, and a phase shifter is configured to receive the impedance matching compensation pulse and to shift a phase of the impedance matching compensation pulse to synchronize the impedance matching compensation pulse to the RF power pulse.

摘要翻译： 脉冲等离子体匹配系统包括：RF匹配盒，被配置为接收由RF电源产生的RF功率脉冲，被配置为执行等离子体阻抗匹配，并且被配置为将RF功率脉冲施加到处理室;以及网络分析器， 以测量在处理室中产生的等离子体的阻抗。 控制器被配置为产生对应于由网络分析器测量的等离子体阻抗值的电容控制信号，其被配置为向RF匹配箱提供电容控制信号，并且被配置为产生阻抗匹配补偿脉冲，并且移相器是 被配置为接收阻抗匹配补偿脉冲并且移动阻抗匹配补偿脉冲的相位以将阻抗匹配补偿脉冲同步到RF功率脉冲。

公开(公告)号：US08222821B2

公开(公告)日：2012-07-17

申请号：US12145850

申请日：2008-06-25

申请人： Keun-Hee Bai ,  Yoon-Jae Kim ,  Yong-Jin Kim

发明人： Keun-Hee Bai ,  Yoon-Jae Kim ,  Yong-Jin Kim

IPC分类号： H05B31/26

CPC分类号： H05H1/46 ,  H01J37/32082 ,  H01J37/32183

摘要： A pulse plasma matching system includes an RF matching box configured to receive an RF power pulse generated by an RF power source, configured to perform a plasma impedance matching, and configured to apply the RF power pulse to a process chamber, and a network analyzer configured to measure an impedance of plasma generated in a process chamber. A controller is configured to generate a capacitance control signal corresponding to a plasma impedance value measured by the network analyzer, configured to supply the capacitance control signal to the RF matching box, and configured to generate an impedance matching compensation pulse, and a phase shifter is configured to receive the impedance matching compensation pulse and to shift a phase of the impedance matching compensation pulse to synchronize the impedance matching compensation pulse to the RF power pulse.

摘要翻译： 脉冲等离子体匹配系统包括：RF匹配盒，被配置为接收由RF电源产生的RF功率脉冲，被配置为执行等离子体阻抗匹配，并且被配置为将RF功率脉冲施加到处理室;以及网络分析器， 以测量在处理室中产生的等离子体的阻抗。 控制器被配置为产生对应于由网络分析器测量的等离子体阻抗值的电容控制信号，其被配置为向RF匹配箱提供电容控制信号，并且被配置为产生阻抗匹配补偿脉冲，并且移相器是 被配置为接收阻抗匹配补偿脉冲并且移动阻抗匹配补偿脉冲的相位以将阻抗匹配补偿脉冲同步到RF功率脉冲。

公开(公告)号：US20080278721A1

公开(公告)日：2008-11-13

申请号：US12151516

申请日：2008-05-07

申请人： Keun-Hee Bai ,  Yong-Jin Kim

发明人： Keun-Hee Bai ,  Yong-Jin Kim

IPC分类号： G01J3/443

CPC分类号： G01J3/443 ,  H01J37/32935 ,  H01J37/32972

摘要： Provided are methods and systems for monitoring a state of a plasma chamber. In the method, an optical characteristic of plasma generated in a plasma chamber including a window is measured in a predetermined measurement wavelength band. A process status index (PSI) is extracted from the measured optical characteristic. A state of the plasma chamber is evaluated by analyzing the extracted PSI. The optical characteristic of the plasma is measured in the predetermined measurement wavelength band in which a transmittance of light passing through the window is substantially independent of a wavelength of the light.

摘要翻译： 提供了用于监测等离子体室的状态的方法和系统。 在该方法中，在预定的测量波长带中测量在包括窗口的等离子体室中产生的等离子体的光学特性。 从测量的光学特性中提取过程状态指数（PSI）。 通过分析所提取的PSI来评估等离子体室的状态。 在通过窗口的光的透射率基本上与光的波长无关的预定测量波长带中测量等离子体的光学特性。

公开(公告)号：US20100151599A1

公开(公告)日：2010-06-17

申请号：US12654184

申请日：2009-12-14

申请人： Keun-Hee Bai ,  Yong-Jin Kim

发明人： Keun-Hee Bai ,  Yong-Jin Kim

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L22/26

摘要： A method of manufacturing a semiconductor device includes depositing material on a wafer in a process chamber to form a thin film on the wafer, a by-product layer being simultaneously formed on an inner part of the process chamber, monitoring a change in thickness or mass of the by-product layer on the inner part of the process chamber during a process in the process chamber by using a QCM installed in the process chamber, and determining an end point of the process in the process chamber based on the monitored change in thickness or mass of the by-product layer in the process chamber.

摘要翻译： 制造半导体器件的方法包括在处理室中的晶片上沉积材料以在晶片上形成薄膜，在处理室的内部同时形成副产物层，监测厚度或质量的变化 通过使用安装在处理室中的QCM在处理室的处理过程中处理室内部的副产物层，以及基于所监测的厚度变化来确定处理室中的处理的终点 或处理室中副产物层的质量。

公开(公告)号：US07705973B2

公开(公告)日：2010-04-27

申请号：US12151516

申请日：2008-05-07

申请人： Keun-Hee Bai ,  Yong-Jin Kim

发明人： Keun-Hee Bai ,  Yong-Jin Kim

IPC分类号： G01J3/443 ,  H05H1/00

CPC分类号： G01J3/443 ,  H01J37/32935 ,  H01J37/32972

摘要： Provided are methods and systems for monitoring a state of a plasma chamber. In the method, an optical characteristic of plasma generated in a plasma chamber including a window is measured in a predetermined measurement wavelength band. A process status index (PSI) is extracted from the measured optical characteristic. A state of the plasma chamber is evaluated by analyzing the extracted PSI. The optical characteristic of the plasma is measured in the predetermined measurement wavelength band in which a transmittance of light passing through the window is substantially independent of a wavelength of the light.

摘要翻译： 提供了用于监测等离子体室的状态的方法和系统。 在该方法中，在预定的测量波长带中测量在包括窗口的等离子体室中产生的等离子体的光学特性。 从测量的光学特性中提取过程状态指数（PSI）。 通过分析所提取的PSI来评估等离子体室的状态。 在通过窗口的光的透射率基本上与光的波长无关的预定测量波长带中测量等离子体的光学特性。

公开(公告)号：US20050282363A1

公开(公告)日：2005-12-22

申请号：US11157435

申请日：2005-06-21

申请人： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

发明人： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/36 ,  H01L21/469 ,  H01L21/60

CPC分类号： H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

摘要： There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

摘要翻译： 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，并且形成硅锗（Si 1-Si） xTi）x牺牲层，其具有等于或高于至少导电线结构的高度的高度，在基底的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US09299700B2

公开(公告)日：2016-03-29

申请号：US14639494

申请日：2015-03-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US20110143532A1

公开(公告)日：2011-06-16

申请号：US12801013

申请日：2010-05-17

申请人： Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

发明人： Keun-Hee Bai ,  Chul-Ho Shin ,  Shin-Hye Kim ,  Sang-Kuk Kim

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31111 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888

摘要： In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

摘要翻译： 在形成半导体单元结构的方法中，可以在半导体衬底上形成第一绝缘层。 可以在第一绝缘层中形成连接图案。 第二和第三绝缘层可以顺序形成在连接图案上。 可以将第三绝缘层蚀刻至少两次，并且可以蚀刻第二绝缘层至少一次以在第二和第三绝缘层中形成通孔。 通孔可能暴露连接图案。

公开(公告)号：US20080020582A1

公开(公告)日：2008-01-24

申请号：US11822058

申请日：2007-07-02

申请人： Keun-Hee Bai

发明人： Keun-Hee Bai

IPC分类号： H01L21/467

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31144 ,  H01L28/91

摘要： In methods of forming an opening in a semiconductor device and methods of manufacturing a semiconductor device, a mask pattern may be formed on a layer to selectively expose the layer through the mask pattern. The layer may be partially etched using the mask pattern as an etching mask and using a first etching gas including carbon under a silicon-containing gas atmosphere until a lower layer beneath the layer is exposed to form a preliminary opening. The layer may be etched using the mask pattern as an etching mask and using a second etching gas until the lower layer is exposed to form an opening through the layer. The layer may be an insulation layer.

摘要翻译： 在形成半导体器件中的开口的方法和制造半导体器件的方法中，可以在层上形成掩模图案，以通过掩模图案选择性地暴露该层。 可以使用掩模图案作为蚀刻掩模来部分地蚀刻该层，并且在含硅气体气氛下使用包含碳的第一蚀刻气体直到层下面的下层暴露以形成初步开口。 可以使用掩模图案作为蚀刻掩模蚀刻该层，并且使用第二蚀刻气体直到下层暴露以形成通过该层的开口。 该层可以是绝缘层。

公开(公告)号：US09755079B2

公开(公告)日：2017-09-05

申请号：US15000495

申请日：2016-01-19

申请人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

发明人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/7848

摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.