公开(公告)号：US6030891A

公开(公告)日：2000-02-29

申请号：US993052

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Guarionex Morales

发明人： Khanh Tran ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76852 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/31058 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案化的后续间隙的下部金属特征电连接。 在填充通孔之前进行真空烘烤以排出在溶剂清洗期间吸收的水，从而减少空隙形成并改进通过完整性。 实施方案包括在约300℃至约400℃的温度下，在不大于约10 -6乇的压力下进行约45秒至约2分钟的真空烘烤，优选在用于沉积的相同工具中进行真空烘烤 阻挡层填充通孔。

公开(公告)号：US5994778A

公开(公告)日：1999-11-30

申请号：US157240

申请日：1998-09-18

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L21/316 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US06281584B1

公开(公告)日：2001-08-28

申请号：US09373482

申请日：1999-08-12

申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L2348

CPC分类号： H01L21/31629 ,  H01L21/76801 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US06444593B1

公开(公告)日：2002-09-03

申请号：US09373483

申请日：1999-08-12

申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L21425

CPC分类号： H01L21/31629 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至 预定深度。

公开(公告)号：US06335273B2

公开(公告)日：2002-01-01

申请号：US09443376

申请日：1999-11-19

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L214763

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US6100192A

公开(公告)日：2000-08-08

申请号：US993892

申请日：1997-12-18

申请人： Guarionex Morales ,  Richard J. Huang

发明人： Guarionex Morales ,  Richard J. Huang

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/28052

摘要： Thin films of tungsten silicide are deposited by CVD on conductive lines under conditions controlled to minimize development of tensile stresses upon subsequent thermal processing, thereby reducing cracking and delamination. Embodiments include reducing the deposition temperature and/or adjusting the gas flow ratio of reactants, such that the as deposited tungsten silicide film does not undergo a significant increase in densification and/or crystallinity upon subsequent deposition of a polycrystalline silicon capping layer.

摘要翻译： 在控制的条件下，通过CVD在导电线上沉积硅化钨薄膜，以便在随后的热处理时最小化拉伸应力的发展，从而减少开裂和分层。 实施方案包括降低沉积温度和/或调节反应物的气体流动比，使得随后沉积多晶硅覆盖层时，沉积的硅化钨膜不会显着增加致密化和/或结晶度。

公开(公告)号：US06211074B1

公开(公告)日：2001-04-03

申请号：US09076584

申请日：1998-05-12

申请人： Richard J. Huang ,  Guarionex Morales

发明人： Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L214763

CPC分类号： H01L27/11521 ,  H01L21/32053 ,  H01L27/115

摘要： Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.

摘要翻译： 提供了在制造非易失性存储器半导体器件中的控制栅极配置期间增加过程控制的方法和布置。 该方法和装置有效地防止在作为非易失性存储单元内的控制栅极结构的一部分的硅化钨层内发生裂纹。 硅化钨层内的裂纹可以通过增加控制栅极配置的电阻来影响存储单元的性能。 所述方法和装置通过使与硅化钨层的沉积相关的温度之间的相对差异和随后的上覆盖层的沉积最小化来防止硅化钨层的破裂。

公开(公告)号：US06436850B1

公开(公告)日：2002-08-20

申请号：US09652132

申请日：2000-08-31

申请人： Guarionex Morales

发明人： Guarionex Morales

IPC分类号： H01L214763

CPC分类号： H01L21/76828 ,  H01L21/3124

摘要： Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.

摘要翻译： 由于多次预金属化除气/除气热处理，多金属化水平半导体器件形成而不降低低k电介质间隙填充材料。 通过采用不长于最长金属沉积步骤和低于电介质材料分解温度的温度的热处理时间间隔，可以显着降低或消除低k材料的劣化。

公开(公告)号：US06265294B1

公开(公告)日：2001-07-24

申请号：US09373084

申请日：1999-08-12

申请人： Stephen Keetai Park ,  Guarionex Morales ,  Bharath Rangarajan ,  Jeff Shields

发明人： Stephen Keetai Park ,  Guarionex Morales ,  Bharath Rangarajan ,  Jeff Shields

IPC分类号： H01L21425

CPC分类号： H01L23/5329 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/76829 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.

摘要翻译： 制造方法减少了由于抗反射涂层（ARC）引起的层间电介质层上的变色量。 本发明利用阻挡层，例如防止抗反射涂层与层间介质层（ILD0）接触的氮化硅（SiN）。 抗反射涂层可以是通过LPCVD或PECVD沉积的氮氧化硅（SiON）。

公开(公告)号：US06265273B1

公开(公告)日：2001-07-24

申请号：US09359502

申请日：1999-07-23

申请人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

发明人： Steven C. Avanzino ,  Stephen Keetai Park ,  Bharath Rangarajan ,  Jeffrey A. Shields ,  Larry Yu Wang ,  Guarionex Morales

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/31116

摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

摘要翻译： 本文公开了一种在集成电路中形成间隔物的方法。 该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。 间隔物具有暴露于直接溅射的最小表面积。