公开(公告)号：US6030891A

公开(公告)日：2000-02-29

申请号：US993052

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Guarionex Morales

发明人： Khanh Tran ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76852 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/31058 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案化的后续间隙的下部金属特征电连接。 在填充通孔之前进行真空烘烤以排出在溶剂清洗期间吸收的水，从而减少空隙形成并改进通过完整性。 实施方案包括在约300℃至约400℃的温度下，在不大于约10 -6乇的压力下进行约45秒至约2分钟的真空烘烤，优选在用于沉积的相同工具中进行真空烘烤 阻挡层填充通孔。

公开(公告)号：US06329718B1

公开(公告)日：2001-12-11

申请号：US09105775

申请日：1998-06-26

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性 在ILD形成期间。

公开(公告)号：US06492258B1

公开(公告)日：2002-12-10

申请号：US09881831

申请日：2001-06-14

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L214763

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，形成不希望的空隙的可能性。 在互连线路中减少。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。 并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

公开(公告)号：US6093635A

公开(公告)日：2000-07-25

申请号：US993124

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

发明人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。 在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

公开(公告)号：US20120325192A1

公开(公告)日：2012-12-27

申请号：US13168632

申请日：2011-06-24

申请人： Loc T. Pham ,  Omar Alonso Macy ,  Khanh Tran

发明人： Loc T. Pham ,  Omar Alonso Macy ,  Khanh Tran

IPC分类号： F41B11/02 ,  F41B11/00

CPC分类号： F41B11/70 ,  F41B11/50 ,  F41B11/72

摘要： A paintball assembly capable of retaining a paintball in a loading chamber using a paintball catcher is disclosed. The paintball assembly includes a loading chamber, a detent, and a bolt. The loading chamber is coupled to a loading port to receive paintballs. In one embodiment, the detent includes a paintball catcher capable of catching the paintball as it is loaded into the loading chamber. In one example, the paintball catcher is a flexible paintball catcher extending into the loading chamber and is able to catch the paintball and hold it in a predefined position. When a trigger is pulled, the bolt pushes the paintball into a firing chamber while the paintball catcher releases the paintball.

摘要翻译： 公开了一种能够使用彩弹捕获器在装载室中保持彩弹的彩弹组件。 彩弹组件包括装载室，制动器和螺栓。 装载室联接到装载口以接收彩弹。 在一个实施例中，制动器包括一个能够在彩弹被装载到装载室中时捕捉彩弹的彩弹捕获器。 在一个示例中，彩弹捕获器是延伸到装载室中的灵活的彩弹捕获器，并且能够捕捉彩弹并将其保持在预定位置。 当扳机被拉动时，螺栓将彩弹球推入射击室，而彩弹捕手则释放彩弹。

公开(公告)号：US07921836B2

公开(公告)日：2011-04-12

申请号：US12436806

申请日：2009-05-07

申请人： Khanh Tran

发明人： Khanh Tran

IPC分类号： F41B11/00

CPC分类号： F41B11/55 ,  F41A9/38 ,  F41B11/52

摘要： A paintball marker includes a main body and a dual feed adapter coupled to the main body. The dual feed adapter has a hollow interior, a top feed port and a bottom feed port. A top feed storage hopper is detachably connected to the dual feed adapter at the top feed port, and a bottom feed storage magazine is detachably connected to the dual feed adapter at the bottom feed port. A sleeve with an opening is rotatable within the dual feed adapter between a first position where the sleeve opening aligns with the top feed port for feeding therethrough a first group of paintballs from the hopper, and a second position where the sleeve opening aligns with the bottom feed port for feeding therethrough a second group of paintballs from the magazine.

摘要翻译： 彩弹标记器包括主体和耦合到主体的双馈进给适配器。 双进给适配器具有中空内部，顶部进料口和底部进料口。 顶部进料储存料斗在顶部进料口处可拆卸地连接到双进料适配器，并且底部进料存储盒可拆卸地连接到底部进料口处的双进料适配器。 具有开口的套筒可在双进给适配器内在第一位置和第二位置之间旋转，第一位置和第二位置之间，其中套筒开口与顶部进料口对准，用于从料斗通过第一组彩弹，以及第二位置，其中套筒开口与底部 馈送端口，用于从盒中馈送第二组彩弹。

公开(公告)号：US06607962B2

公开(公告)日：2003-08-19

申请号：US09925945

申请日：2001-08-09

申请人： Viktor Zekeriya ,  Khanh Tran

发明人： Viktor Zekeriya ,  Khanh Tran

IPC分类号： H01L2120

CPC分类号： H01L24/05 ,  H01L23/5228 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.

摘要翻译： 形成薄膜电阻器触点的方法包括蚀刻停止材料，以保护下面的薄膜电阻器免受后来的干蚀刻工艺以形成对薄膜电阻器的接触开口。 更具体地，该方法包括形成薄膜电阻器，在薄膜电阻器上形成第一电介质层，形成穿过第一电介质层的第一开口以暴露薄膜电阻器的下面部分，在该薄膜电阻器的内部形成蚀刻停止 第一介电层的第一开口，在蚀刻停止层和第一介电层上方形成第二介电层，形成通过第二介电层的第二开口以暴露蚀刻停止层的下面部分，并在其内形成金属塞 第二接触开口，其中金属插塞通过蚀刻停止与薄膜电阻器电接触。 或者，在绝缘蚀刻停止的情况下，穿过介电层的第二开口通过蚀刻停止，并且在第二接触开口内形成金属插塞，其中金属插塞与薄膜直接电接触 电阻。

公开(公告)号：US06351013B1

公开(公告)日：2002-02-26

申请号：US09352339

申请日：1999-07-13

申请人： Scott Luning ,  David Wu ,  Khanh Tran

发明人： Scott Luning ,  David Wu ,  Khanh Tran

IPC分类号： H01L31062

CPC分类号： H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

摘要： The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

摘要翻译： 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US6043147A

公开(公告)日：2000-03-28

申请号：US993119

申请日：1997-12-18

申请人： Robert C. Chen ,  Jeffrey A. Shields ,  Robert Dawson ,  Khanh Tran

发明人： Robert C. Chen ,  Jeffrey A. Shields ,  Robert Dawson ,  Khanh Tran

IPC分类号： C23C16/40 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/316

CPC分类号： H01L21/02134 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31058 ,  H01L21/3124 ,  H01L21/76801

摘要： Patterned metal layers are gap filled with HSQ and passivated to stabilize the dielectric constant of the HSQ substantially at the as-deposited value prior to oxide deposition by PECVD and planarization. Passivation and stabilization are effected by treating the as--deposited HSQ layer in a silane (SiH.sub.4) containing plasma.

摘要翻译： 图案化的金属层是填充有HSQ的间隙，并且被钝化以在通过PECVD和平坦化的氧化物沉积之前基本上以沉积值稳定HSQ的介电常数。 通过在含硅烷（SiH 4）的等离子体中处理沉积的HSQ层来实现钝化和稳定化。

公开(公告)号：US5582881A

公开(公告)日：1996-12-10

申请号：US602200

申请日：1996-02-16

申请人： Paul R. Besser ,  Raymond Lee ,  Khanh Tran

发明人： Paul R. Besser ,  Raymond Lee ,  Khanh Tran

IPC分类号： C23C14/06 ,  C23C14/16 ,  C23C14/56 ,  H05H1/24

CPC分类号： C23C14/165 ,  C23C14/0641 ,  C23C14/568

摘要： A single chamber of a vapor deposition system is used to deposit both Ti and TiN, subsequent to deposition of Al or Al alloy. Because such layers are deposited in the same chamber, the process requires fewer handling steps than the conventional process, thereby increasing throughput. Still further, only three physical vapor deposition chambers of the four of the apparatus are used, thereby allowing the fourth chamber to be used for other deposition.

摘要翻译： 在沉积Al或Al合金之后，使用单室蒸镀系统沉积Ti和TiN。 因为这样的层被沉积在相同的室中，所以该方法比常规方法需要较少的处理步骤，从而增加产量。 此外，仅使用四个设备中的三个物理气相沉积室，从而允许第四室用于其他沉积。