公开(公告)号：US06884670B2

公开(公告)日：2005-04-26

申请号：US10028429

申请日：2001-12-28

申请人： Koichi Hashimoto ,  Daisuke Matsunaga ,  Masaaki Aoyama

发明人： Koichi Hashimoto ,  Daisuke Matsunaga ,  Masaaki Aoyama

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3213 ,  H01L21/335 ,  H01L21/336 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/0332 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/76838 ,  Y10S438/926

摘要： A method of manufacturing a semiconductor device having an insulated gate type field effect transistor. A gate insulating film, a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed therebetween, an interlayer insulating film, and a wiring layer connected to the gate electrode layer, are formed on a semiconductor substrate in the order recited. A conductive material layer and a resist layer are formed on the wiring layer. The resist layer is patterned to form a resist mask forming a wiring pattern having an antenna ratio of about ten times or more of the predetermined area of the gate electrode layer. At least the conductive material layer is plasma-etched by using the resist mask as an etching mask, and thereafter, the resist mask is removed and the wiring layer is plasma-etched.

摘要翻译： 一种制造具有绝缘栅型场效应晶体管的半导体器件的方法。 栅极绝缘膜，具有预定面积的面对半导体衬底的栅电极层，栅极绝缘膜插入其间，层间绝缘膜和连接到栅极电极层的布线层形成在半导体衬底上 命令叙述。 在布线层上形成导电材料层和抗蚀剂层。 对抗蚀剂层进行图案化以形成抗蚀剂掩模，形成天线比为栅电极层的预定面积的大约十倍或更多的布线图案。 至少通过使用抗蚀剂掩模作为蚀刻掩模来等离子体蚀刻导电材料层，然后去除抗蚀剂掩模，并且对该布线层进行等离子体蚀刻。

公开(公告)号：US06376388B1

公开(公告)日：2002-04-23

申请号：US08787451

申请日：1997-01-22

申请人： Koichi Hashimoto ,  Daisuke Matsunaga ,  Masaaki Aoyama

发明人： Koichi Hashimoto ,  Daisuke Matsunaga ,  Masaaki Aoyama

IPC分类号： H01L21302

CPC分类号： H01L21/0332 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/76838 ,  Y10S438/926

摘要： A method of manufacturing a semiconductor device having an insulated gate type field effect transistor. A gate insulating film, a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed therebetween, an interlayer insulating film, and a wiring layer connected to the gate electrode layer, are formed on a semiconductor substrate in the order recited. A conductive material layer and a resist layer are formed on the wiring layer. The resist layer is patterned to form a resist mask forming a wiring pattern having an antenna ratio of about ten times or more of the predetermined area of the gate electrode layer. At least the conductive material layer is plasma-etched by using the resist mask as an etching mask, and thereafter, the resist mask is removed and the wiring layer is plasma-etched.

摘要翻译： 一种制造具有绝缘栅型场效应晶体管的半导体器件的方法。 栅极绝缘膜，具有预定面积的面对半导体衬底的栅电极层，栅极绝缘膜插入其间，层间绝缘膜和连接到栅极电极层的布线层形成在半导体衬底上 命令叙述。 在布线层上形成导电材料层和抗蚀剂层。 对抗蚀剂层进行图案化以形成抗蚀剂掩模，形成天线比为栅电极层的预定面积的大约十倍或更多的布线图案。 至少通过使用抗蚀剂掩模作为蚀刻掩模来等离子体蚀刻导电材料层，然后去除抗蚀剂掩模，并且对该布线层进行等离子体蚀刻。

公开(公告)号：US5656128A

公开(公告)日：1997-08-12

申请号：US216963

申请日：1994-03-24

申请人： Koichi Hashimoto ,  Toshiyuki Ohtsuka ,  Fumihiko Shinpuku ,  Daisuke Matsunaga ,  Takayuki Enda

发明人： Koichi Hashimoto ,  Toshiyuki Ohtsuka ,  Fumihiko Shinpuku ,  Daisuke Matsunaga ,  Takayuki Enda

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/306

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/31138 ,  H01L21/32137 ,  Y10S438/95 ,  Y10S438/952

摘要： A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.

摘要翻译： 具有在形成在基板上的图案化层上形成非晶碳膜的步骤的图案形成方法，在非晶碳膜上形成光致抗蚀剂膜的步骤，选择性地曝光和显影光致抗蚀剂膜以形成光致抗蚀剂图案的步骤 以及通过使用光致抗蚀剂膜作为蚀刻掩模来连续干法蚀刻非晶碳膜和图案化层的步骤。 通过溅射形成的非晶碳膜的期望光学常数可以通过控制衬底温度和其它参数来获得。

公开(公告)号：US6007732A

公开(公告)日：1999-12-28

申请号：US841787

申请日：1997-05-05

申请人： Koichi Hashimoto ,  Toshiyuki Ohtsuka ,  Fumihiko Shinpuku ,  Daisuke Matsunaga ,  Takayuki Enda

发明人： Koichi Hashimoto ,  Toshiyuki Ohtsuka ,  Fumihiko Shinpuku ,  Daisuke Matsunaga ,  Takayuki Enda

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/31138 ,  H01L21/32137 ,  Y10S438/952

摘要： A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.

摘要翻译： 具有在形成在基板上的图案化层上形成非晶碳膜的步骤的图案形成方法，在非晶碳膜上形成光致抗蚀剂膜的步骤，选择性地曝光和显影光致抗蚀剂膜以形成光致抗蚀剂图案的步骤 以及通过使用光致抗蚀剂膜作为蚀刻掩模来连续干法蚀刻非晶碳膜和图案化层的步骤。 通过溅射形成的非晶碳膜的期望光学常数可以通过控制衬底温度和其它参数来获得。

公开(公告)号：US09230872B2

公开(公告)日：2016-01-05

申请号：US13805039

申请日：2011-06-17

申请人： Koichi Hashimoto

发明人： Koichi Hashimoto

IPC分类号： H01L23/29 ,  C03C8/02 ,  C03C3/068 ,  C03C3/095 ,  C03C8/24 ,  H01L33/56

CPC分类号： H01L23/291 ,  C03C3/068 ,  C03C3/095 ,  C03C8/24 ,  H01L33/56 ,  H01L2924/0002 ,  H01L2924/00

摘要： The technical task of the present invention is to provide a lead-free glass for semiconductor encapsulation, which is easy to automate an appearance inspection, and furthermore, has excellent refinability and encapsulatability of semiconductor devices. In the lead-free glass for semiconductor encapsulation according to the present invention, a temperature at which the viscosity of glass is 106 dPa·s is 670° C. or lower, and, as a glass composition, the content of CeO2 is from 0.01 to 6% by mass, and the content of Sb2O3 is 0.1% by mass or less.

摘要翻译： 本发明的技术任务是提供一种用于半导体封装的无铅玻璃，其容易自动进行外观检查，此外，具有优异的可熔性和半导体器件的可封装性。 在本发明的半导体封装用无铅玻璃中，玻璃粘度为106dPa·s的温度为670℃以下，作为玻璃组合物，CeO 2的含量为0.01 〜6质量％，Sb 2 O 3的含量为0.1质量％以下。

公开(公告)号：US08933463B2

公开(公告)日：2015-01-13

申请号：US13780876

申请日：2013-02-28

申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H03K17/14 ,  H01L29/45

CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

摘要： A semiconductor element including an MISFET exhibits diode characteristics in a reverse direction through an epitaxial channel layer. The semiconductor element includes: a silicon carbide semiconductor substrate of a first conductivity type, semiconductor layer of the first conductivity type, body region of a second conductivity type, source region of the first conductivity type, epitaxial channel layer in contact with the body region, source electrode, gate insulating film, gate electrode and drain electrode. If the voltage applied to the gate electrode is smaller than a threshold voltage, the semiconductor element functions as a diode wherein current flows from the source electrode to the drain electrode through the epitaxial channel layer. The absolute value of the turn-on voltage of this diode is smaller than the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括MISFET的半导体元件通过外延沟道层在相反方向上表现出二极管特性。 半导体元件包括：第一导电类型的碳化硅半导体衬底，第一导电类型的半导体层，第二导电类型的主体区域，第一导电类型的源极区域，与身体区域接触的外延沟道层， 源电极，栅极绝缘膜，栅电极和漏电极。 如果施加到栅电极的电压小于阈值电压，则半导体元件用作二极管，其中电流从源电极通过外延沟道层流到漏电极。 该二极管的导通电压的绝对值小于由体区和第一碳化硅半导体层形成的体二极管的导通电压。

公开(公告)号：US20130058029A1

公开(公告)日：2013-03-07

申请号：US13557635

申请日：2012-07-25

申请人： Hideyoshi Ootani ,  Kazuhide Sato ,  Makoto Honda ,  Koichi Hashimoto ,  Tomoyuki Kinoshita ,  Masaaki Yamamoto ,  Kobun Takahashi ,  Hiroshi Morimoto

发明人： Hideyoshi Ootani ,  Kazuhide Sato ,  Makoto Honda ,  Koichi Hashimoto ,  Tomoyuki Kinoshita ,  Masaaki Yamamoto ,  Kobun Takahashi ,  Hiroshi Morimoto

IPC分类号： G06F1/20

CPC分类号： F24F3/044 ,  H05K7/1497 ,  H05K7/20745

摘要： A data center is disclosed that includes a container; a server; a rack installed within the container and storing the server; and a curtain fixed to at least one point of the rack or the container and separating an internal space of the container between a cold side and a hot side; wherein the rack is configured to enable the circulation of air from the cold side to the hot side. The curtain is fixed by a removable clamping mechanism. The data center further includes a modular refrigeration unit configured to attach to the container and direct cold air into the cold area. At least one prop is positioned below a bottom of the housing and connected to a container bottom, the prop is configured to absorb vibration of the container or housing.

摘要翻译： 公开了一种包括容器的数据中心; 一个服务器 安装在容器内并存储服务器的机架; 以及窗帘，其固定在所述架子或所述容器的至少一个点上，并且在所述冷侧和所述热侧之间分离所述容器的内部空间; 其中，所述支架构造成能够使空气从所述冷侧循环到所述热侧。 窗帘通过可拆卸的夹紧机构固定。 数据中心还包括模块化制冷单元，其被配置为附接到容器并将冷空气引导到冷区域中。 至少一个支柱位于壳体的底部下方并连接到容器底部，支撑构造成吸收容器或壳体的振动。

公开(公告)号：US08283973B2

公开(公告)日：2012-10-09

申请号：US13389555

申请日：2010-08-09

申请人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

发明人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

IPC分类号： G05F3/02

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7838 ,  H02M7/5387 ,  Y02B70/1483

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的半导体层20，第一导电类型的体区30 第二导电类型，第一导电类型的源极和漏极区域40和75，与主体区域接触的外延沟道层50，源极和漏极电极45和70，栅极绝缘膜60和栅电极65.如果 施加到MISFET的栅电极的电压小于阈值电压，半导体元件100用作二极管，其中电流通过外延沟道层50从源电极45流到漏极70。绝对值 该二极管的导通电压小于由体区和第一硅碳化物形成的体二极管的导通电压的导通电压 e半导体层。

公开(公告)号：US20120057386A1

公开(公告)日：2012-03-08

申请号：US13266271

申请日：2010-04-28

申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

IPC分类号： H02M7/537 ,  H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的碳化硅半导体衬底10，半导体层20 第一导电类型的体区30，第一导电类型的源极区40，与体区接触的外延沟道层50，源电极45，栅极绝缘膜60， 栅电极65和漏电极70.如果施加到MISFET的栅电极的电压小于阈值电压，则半导体元件100用作二极管，其中电流从源电极45流到漏电极70通过 外延沟道层50.该二极管的导通电压的绝对值小于体二的导通电压的绝对值 由所述体区和所述第一碳化硅半导体层形成。

公开(公告)号：US07968380B2

公开(公告)日：2011-06-28

申请号：US12489561

申请日：2009-06-23

申请人： Koichi Hashimoto

发明人： Koichi Hashimoto

IPC分类号： H01L21/00 ,  C03C3/076 ,  C03C3/089

CPC分类号： C03C8/02 ,  C03C8/08 ,  H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor encapsulation material of the present invention contains a glass for metal coating which has a strain point of 480° C. or higher, a temperature corresponding to a viscosity of 104 dPa·s of 1,100° C. or lower, and a thermal expansion coefficient at 30 to 380° C. of 70×10−7 to 110×10−7/° C. The semiconductor encapsulation material of the present invention contains no environmentally harmful substances, has a heat resistance temperature as high as 500° C. or above, and can be used for the encapsulation of metals susceptible to oxidation, e.g., Dumet.

摘要翻译： 本发明的半导体封装材料含有应变点为480℃以上的金属涂层用玻璃，对应于粘度为104dPa·s的温度为1100℃以下的温度，热膨胀 30〜380℃的系数为70×10-7〜110×10-7 /℃。本发明的半导体封装材料不含环境有害物质，耐热温度高达500℃。 或以上，并且可用于包封易受氧化的金属，例如Dumet。