公开(公告)号：US5534864A

公开(公告)日：1996-07-09

申请号：US12759

申请日：1993-02-03

Applicant: Koichi Ono ,  Yoshito Nejime ,  Etsuji Yamamoto

Inventor： Koichi Ono ,  Yoshito Nejime ,  Etsuji Yamamoto

IPC: H03M1/14 ,  H03M1/06 ,  H03M1/16

CPC classification number: H03M1/0695 ,  H03M1/167

Abstract: A pipelined A/D converter which minimizes differential non-linearity by preventing mismatching between converting stages. The A/D converter includes a plurality of converting stages connected in a cascade form wherein each of the converting stages includes an ADC unit for converting an analog input into a digital output. The digital outputs from said converting stages form a conversion output. Each preceding converting stage except a last converting stage further includes an amplifier for deriving and amplifying a conversion residue representing a quantization error resulting from the conversion performed by the preceding converting stage based on the digital output outputted by the ADC unit of the preceding converting stage and the analog input inputted to the preceding converting stage. The amplified conversion residue from the preceding converting stage is supplied as an analog input to a succeeding converting stage. A connector is provided for connecting the amplifier of the preceding converting stage to a node in the ADC unit of the succeeding converting stage. The node provides a base voltage to the ADC unit of the succeeding converting stage.

Abstract translation: 一种流水线A / D转换器，通过防止转换级之间的失配使差分非线性最小化。 A / D转换器包括以级联形式连接的多个转换级，其中每个转换级包括用于将模拟输入转换为数字输出的ADC单元。 来自所述转换级的数字输出形成转换输出。 除了最后的转换级之外的每个前一转换级还包括放大器，用于根据由前一转换级的ADC单元输出的数字输出，导出并放大表示由前一转换级进行的转换而产生的量化误差的转换余数，以及 输入到前一转换级的模拟输入。 来自前一转换级的放大的转换余数作为模拟输入提供给后续转换级。 提供连接器，用于将前一转换级的放大器连接到后续转换级的ADC单元中的节点。 节点为后续转换级的ADC单元提供基极电压。

公开(公告)号：US5138203A

公开(公告)日：1992-08-11

申请号：US342328

申请日：1989-04-24

Applicant: Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

Inventor： Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

IPC: H03M1/36 ,  H03K17/16 ,  H03K17/60 ,  H03K19/0175 ,  H03M1/06

CPC classification number: H03M1/06 ,  H03K17/16 ,  H03K17/603 ,  H03M1/365

Abstract: An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z.sub.0 .sqroot.L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z.sub.0, and the signal source has output impedance equal to the characteristic impedance Z.sub.0.

Abstract translation: 公开了一种集成电路，其包括具有相同输入阻抗的多个电路，以规则的间隔布置并且施加了来自单个信号源的信号，其中输入阻抗基本上是电容性的，信号线的特性阻抗连接到 用于将信号发送到电路的信号源由Z0 2ROOT L / C给出，其中L表示每个电路的信号线的电感，C表示每个电路的信号线的寄生电容的组合电容， 每个电路的输入电容，信号线由具有等于特性阻抗Z0的阻抗的电路元件端接，并且信号源具有等于特性阻抗Z0的输出阻抗。

公开(公告)号：US4866444A

公开(公告)日：1989-09-12

申请号：US154086

申请日：1988-02-09

Applicant: Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

Inventor： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

IPC: H03M1/36 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0809 ,  H03M1/365

Abstract: A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.

Abstract translation: 闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。 一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。 转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。 当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于 生成特定输出的比较器所属的块的比较器。

公开(公告)号：US20140023566A1

公开(公告)日：2014-01-23

申请号：US14110086

申请日：2012-03-12

Applicant: Tomoki Nakano ,  Koichi Ono

Inventor： Tomoki Nakano ,  Koichi Ono

IPC: B01L3/00

CPC classification number: B01L3/56 ,  B01J19/0093 ,  B01J19/123 ,  B01J2219/00783 ,  B01J2219/00808 ,  B01J2219/00833 ,  B01J2219/00853 ,  B01J2219/00988 ,  B01L3/502707 ,  B01L3/502715 ,  B01L7/525 ,  B01L2200/0689 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/0887 ,  B01L2300/1827 ,  B01L2400/0406 ,  B01L2400/0421 ,  B29C65/4855 ,  B29C66/112 ,  B29C66/114 ,  B29C66/53461 ,  B29C66/71 ,  B29C66/7352 ,  B29K2707/04 ,  B29L2031/756 ,  B81C3/001 ,  G01N27/403 ,  G01N27/44704 ,  G01N27/44791 ,  B29K2067/003 ,  B29K2069/00 ,  B29K2033/12 ,  B29K2027/06 ,  B29K2023/12 ,  B29K2071/00 ,  B29K2023/06

Abstract: The present invention relates to a microchannel chip capable of preventing fluid leakage caused by a lamination defect. Bottomed first regions, second regions, and third regions are formed by joining a film to a lower surface of the chip main body of a microchannel chip. The third regions are in communication with the second regions and are formed on carbon inks. The third regions are formed wider than the carbon inks are. The third regions are filled with an electroconductive adhesive.

Abstract translation: 微通道芯片技术领域本发明涉及能够防止层叠缺陷引起的液体泄漏的微通道芯片。 通过将薄膜连接到微通道芯片的芯片主体的下表面而形成底部的第一区域，第二区域和第三区域。 第三区域与第二区域连通并且形成在碳墨水上。 第三区域形成为比碳墨水更宽。 第三区域填充有导电粘合剂。

公开(公告)号：US20110001648A1

公开(公告)日：2011-01-06

申请号：US12439757

申请日：2007-09-04

Applicant: Takeshi Ohkawa ,  Koichi Ono ,  Kouji Matsuura ,  Yukitosi Yamasita ,  Junji Toyomura ,  Shogo Nakamura ,  Norifimi Kanagawa

Inventor： Takeshi Ohkawa ,  Koichi Ono ,  Kouji Matsuura ,  Yukitosi Yamasita ,  Junji Toyomura ,  Shogo Nakamura ,  Norifimi Kanagawa

IPC: H03M1/12 ,  H03F3/68

CPC classification number: H03M1/0863 ,  H03M1/0682 ,  H03M1/141 ,  H03M1/205 ,  H03M1/365

Abstract: A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).

Abstract translation: 折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负担，并且可以防止电路面积的增加。 该电路包括产生多个差分电压作为参考电压的参考电压产生电路和将多个参考电压之间的差分电压与模拟输入电压转换成差分电流的多个放大电路，并输出这些差分电流。 放大电路的输出端交替连接。 每个放大电路由具有共源共栅输出晶体管（145,146）的差分放大器电路构成。 在共源共栅输出晶体管（145,146）的两个源之间提供与控制时钟同步导通的开关（144）。

公开(公告)号：US07748410B2

公开(公告)日：2010-07-06

申请号：US11710167

申请日：2007-02-23

Applicant: Koichi Ono

Inventor： Koichi Ono

IPC: F15C1/04

CPC classification number: B01L3/502746 ,  B01L2200/0684 ,  B01L2300/0816 ,  B01L2300/0861 ,  B01L2400/0406 ,  B01L2400/0688 ,  B01L2400/086 ,  Y10T137/218 ,  Y10T137/2224

Abstract: A first liquid fed into a first flow passage 6 of a fluid handling apparatus travels to the open end thereof on the side of a second flow passage 7 due to capillarity. The movement of the first liquid is uniformed on the cross section of the flow passage by the function of a capillarity promoting portion 220 or 230 of the bottom 21 of the first flow passage 6. Then, the movement of a second liquid fed into the second flow passage 7 is uniformed on the cross section of the flow passage by the function of the capillarity promoting portion 220 or 230 of the bottom 21 of the second flow passage 7. Thus, the movement of the front end of the second liquid is substantially uniformed to surely extrude gas from the second flow passage 7 to the outside via a fourth flow passage 10.

Abstract translation: 进入流体处理装置的第一流动通道6的第一液体由于毛细作用而行进到第二流动通道7侧的开口端。 通过第一流动通道6的底部21的毛细作用促进部分220或230的作用，第一液体的运动在流动通道的横截面上是均匀的。然后，进入第二流体的第二液体的运动 通过第二流动通道7的底部21的毛细作用促进部分220或230的作用，流动通道7在流动通道的横截面上均匀。因此，第二液体的前端的运动基本上是均匀的 以确定地将第二流路7的气体经由第四流路10挤出到外部。

公开(公告)号：US07696917B2

公开(公告)日：2010-04-13

申请号：US11798098

申请日：2007-05-10

Applicant: Kouji Matsuura ,  Koichi Ono ,  Kiyoshi Makigawa

Inventor： Kouji Matsuura ,  Koichi Ono ,  Kiyoshi Makigawa

IPC: H03M1/36

CPC classification number: H03M7/165

Abstract: An encode circuit includes a digital average unit that receives cyclic thermometer codes or standard thermometer codes, and that reduces a bubble error in the received thermometer codes by a majority vote rule, a logical boundary detection unit that detects a logical boundary in the thermometer codes output from the digital average unit, and an encoder unit that generates output codes based on output signals from the logical boundary detection unit.

Abstract translation: 编码电路包括接收循环温度计代码或标准温度计代码的数字平均单元，并且通过多数投票规则减少所接收的温度计代码中的气泡误差;逻辑边界检测单元，其检测温度计代码输出中的逻辑边界 以及编码器单元，其基于来自逻辑边界检测单元的输出信号生成输出代码。

公开(公告)号：US20080219690A1

公开(公告)日：2008-09-11

申请号：US11812025

申请日：2007-06-14

Applicant: Koichi Ono

Inventor： Koichi Ono

IPC: G03G15/00

CPC classification number: G03G15/655 ,  G03G2215/00523

Abstract: The image forming method for executing the proof printing based on a printing job for printing images on recording sheets including a sheet has a step 1) of selecting an substitutive sheet to be used in place of a tab sheet specified in the printing job, and a step 2) of giving an instruction to print a tab sheet image to be printed on the tab of the tab sheet and an outline image representing at least a portion of the tab sheet, on the substitutive paper selected in the step 1).

Abstract translation: 用于执行基于用于在包括纸张的记录纸上打印图像的打印作业的证明打印的图像形成方法具有选择要用于代替在打印作业中指定的标签页的替代纸的步骤1），以及 在步骤1）中选择的替代纸上给出打印要在该标签页的标签上打印的标签页图像和表示标签页的至少一部分的轮廓图像的指令。

公开(公告)号：US07329170B2

公开(公告)日：2008-02-12

申请号：US11366238

申请日：2006-03-02

Applicant: Koichi Ono ,  Tetsuo Shimomura ,  Masahiko Nakamori ,  Takatoshi Yamada ,  Shigeru Komai ,  Masayuki Tsutsumi

Inventor： Koichi Ono ,  Tetsuo Shimomura ,  Masahiko Nakamori ,  Takatoshi Yamada ,  Shigeru Komai ,  Masayuki Tsutsumi

IPC: B24B1/00

CPC classification number: B24B37/26 ,  B24B37/22 ,  B24D3/28 ,  B24D11/001 ,  B24D11/008

Abstract: A method of producing a polishing pad having a polishing layer is characterized in that the polishing layer is produced by a photolithographic method including: forming a sheet molding from a curing composition containing at least an initiator and an energy ray-reactive compound to be cured with energy rays; exposing the sheet molding to energy rays to induce modification thereof, to change the solubility of the sheet molding in a solvent; and developing the sheet molding after irradiation with energy rays, to partially remove the curing composition with a solvent thereby forming a concave and convex pattern at least one surface.

Abstract translation: 一种制造具有抛光层的抛光垫的方法的特征在于，抛光层通过光刻法制造，包括：由至少含有引发剂和能量射线反应性化合物的固化组合物形成片状模制品，以使其固化 能量射线 将片材模制物暴露于能量射线以引起其修饰，以改变片材模制品在溶剂中的溶解度; 并且在用能量射线照射之后显影片材成型体，用溶剂部分地除去固化组合物，从而在至少一个表面上形成凹凸图案。

公开(公告)号：US20070262887A1

公开(公告)日：2007-11-15

申请号：US11798098

申请日：2007-05-10

Applicant: Kouji Matsuura ,  Koichi Ono ,  Kiyoshi Makigawa

Inventor： Kouji Matsuura ,  Koichi Ono ,  Kiyoshi Makigawa

IPC: H03M7/00

CPC classification number: H03M7/165

Abstract: An encode circuit includes a digital average unit that receives cyclic thermometer codes or standard thermometer codes, and that reduces a bubble error in the received thermometer codes by a majority vote rule, a logical boundary detection unit that detects a logical boundary in the thermometer codes output from the digital average unit, and an encoder unit that generates output codes based on output signals from the logical boundary detection unit.

Abstract translation: 编码电路包括接收循环温度计代码或标准温度计代码的数字平均单元，并且通过多数投票规则减少所接收的温度计代码中的气泡误差;逻辑边界检测单元，其检测温度计代码输出中的逻辑边界 以及编码器单元，其基于来自逻辑边界检测单元的输出信号生成输出代码。