公开(公告)号：US20140035619A1

公开(公告)日：2014-02-06

申请号：US13622015

申请日：2012-09-18

申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

IPC分类号： G11C11/34 ,  H01L21/425 ,  H03K19/177

CPC分类号： H01L27/11803 ,  G11C16/04 ,  G11C16/0441 ,  G11C16/10 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H03K19/17764 ,  H03K19/17792

摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.

摘要翻译： 根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和 第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域 每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

公开(公告)号：US08908408B2

公开(公告)日：2014-12-09

申请号：US13613701

申请日：2012-09-13

申请人： Kosuke Tatsumura ,  Masato Oda ,  Atsuhiro Kinoshita ,  Koichiro Zaitsu ,  Mari Matsumoto ,  Shinichi Yasuda

发明人： Kosuke Tatsumura ,  Masato Oda ,  Atsuhiro Kinoshita ,  Koichiro Zaitsu ,  Mari Matsumoto ,  Shinichi Yasuda

IPC分类号： G11C15/00

CPC分类号： H03K19/17728 ,  G11C15/04 ,  G11C15/046 ,  H03K19/17712

摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

公开(公告)号：US08873287B2

公开(公告)日：2014-10-28

申请号：US13606166

申请日：2012-09-07

申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

IPC分类号： G11C16/12 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094

CPC分类号： H03K19/094 ,  H03K19/17728

摘要： A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括第一和第二单元，第一和第二单元中的每一个包括：具有第一至第三端子的第一存储器，第三端子接收控制信号; 连接到源极/漏极之一到第二端子的第一晶体管; 以及第二晶体管的栅极连接到第一晶体管的源极/漏极中的另一个的第二晶体管，第一单元中的第一存储器的第三端子和第二单元中的第一存储器的第三端子共同连接。 当第一单元中的第一存储器进行写入时，第三端子连接到产生写入电压的写入电源，第一和第二单元中的第一端子连接到地电源和写入禁止电源 写禁止电压。

公开(公告)号：US08860459B2

公开(公告)日：2014-10-14

申请号：US13622015

申请日：2012-09-18

申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto

IPC分类号： H03K19/177

CPC分类号： H01L27/11803 ,  G11C16/04 ,  G11C16/0441 ,  G11C16/10 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H03K19/17764 ,  H03K19/17792

摘要： According to one embodiment, a semiconductor integrated circuit includes nonvolatile memory areas, each includes a first nonvolatile memory transistor, a second nonvolatile memory transistor and an output line, the first nonvolatile memory transistor includes a first source diffusion region, a first drain diffusion region and a first control gate electrode, the second nonvolatile memory transistor includes a second source diffusion region, a second drain diffusion region and a second control gate electrode, the output line connected the first drain diffusion region and the second drain diffusion region, and logic transistor areas, each includes a logic transistor, the logic transistor includes a third source diffusion region, a third drain diffusion region and a first gate electrode.

摘要翻译： 根据一个实施例，半导体集成电路包括非易失性存储区域，每个包括第一非易失性存储晶体管，第二非易失性存储晶体管和输出线，第一非易失性存储晶体管包括第一源极扩散区，第一漏极扩散区和 第一控制栅极，第二非易失性存储晶体管包括第二源极扩散区，第二漏极扩散区和第二控制栅电极，连接第一漏极扩散区域和第二漏极扩散区域的输出线以及逻辑晶体管区域 每个都包括逻辑晶体管，逻辑晶体管包括第三源极扩散区，第三漏极扩散区和第一栅电极。

公开(公告)号：US08842475B2

公开(公告)日：2014-09-23

申请号：US13603666

申请日：2012-09-05

申请人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

发明人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

IPC分类号： G11C11/34

CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。

公开(公告)号：US20130076392A1

公开(公告)日：2013-03-28

申请号：US13606166

申请日：2012-09-07

申请人： Koichiro ZAITSU ,  Kosuke Tatsumura ,  Mari Matsumoto

发明人： Koichiro ZAITSU ,  Kosuke Tatsumura ,  Mari Matsumoto

IPC分类号： H03K19/094

CPC分类号： H03K19/094 ,  H03K19/17728

摘要： A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

摘要翻译： 根据实施例的非易失性可编程逻辑开关包括第一和第二单元，第一和第二单元中的每一个包括：具有第一至第三端子的第一存储器，第三端子接收控制信号; 连接到源极/漏极之一到第二端子的第一晶体管; 以及第二晶体管的栅极连接到第一晶体管的源极/漏极中的另一个的第二晶体管，第一单元中的第一存储器的第三端子和第二单元中的第一存储器的第三端子共同连接。 当第一单元中的第一存储器进行写入时，第三端子连接到产生写入电压的写入电源，第一和第二单元中的第一端子连接到地电源和写入禁止电源 写禁止电压。

公开(公告)号：US08829594B2

公开(公告)日：2014-09-09

申请号：US13469867

申请日：2012-05-11

申请人： Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

发明人： Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

摘要翻译： 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US20130307054A1

公开(公告)日：2013-11-21

申请号：US13606292

申请日：2012-09-07

申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

IPC分类号： H01L27/105

CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

公开(公告)号：US20130134499A1

公开(公告)日：2013-05-30

申请号：US13469867

申请日：2012-05-11

申请人： Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

发明人： Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

摘要翻译： 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US08629690B2

公开(公告)日：2014-01-14

申请号：US13605646

申请日：2012-09-06

申请人： Mari Matsumoto ,  Kosuke Tatsumura ,  Koichiro Zaitsu

发明人： Mari Matsumoto ,  Kosuke Tatsumura ,  Koichiro Zaitsu

IPC分类号： H03K19/173 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0441 ,  G11C16/3418 ,  H03K19/1776

摘要： One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire.

摘要翻译： 一个实施例提供了一种可编程逻辑器件，其中逻辑开关包括：第一存储器，其具有连接到第一线的第一端子，连接到第二线的第二端子和连接到第三线的第三端子; 第二存储器，具有连接到第一线的第四端子，连接到第四线的第五端子和连接到第五线的第六端子; 以及具有连接到第一端子的栅极的通过晶体管，以及分别连接到第六线和第七线的源极和漏极。 第一选择栅极晶体管的源极或漏极连接第六导线，第二选择栅极晶体管的源极或漏极连接到第七导线。