公开(公告)号：US08432186B1

公开(公告)日：2013-04-30

申请号：US13484639

申请日：2012-05-31

申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

IPC分类号： H03K19/173

CPC分类号： H03K19/018585 ,  G11C5/146 ,  G11C16/10 ,  G11C16/12 ,  H03K19/1737

摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

摘要翻译： 一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于 擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入 低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

公开(公告)号：US08829594B2

公开(公告)日：2014-09-09

申请号：US13469867

申请日：2012-05-11

申请人： Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

发明人： Kosuke Tatsumura ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

摘要翻译： 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US20130134499A1

公开(公告)日：2013-05-30

申请号：US13469867

申请日：2012-05-11

申请人： Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

发明人： Kosuke TATSUMURA ,  Kiwamu Sakuma ,  Koichiro Zaitsu ,  Mari Matsumoto

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0441 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.

摘要翻译： 根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。 当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值 第二非易失性存储晶体管的电压降低。

公开(公告)号：US20130069134A1

公开(公告)日：2013-03-21

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US08610196B2

公开(公告)日：2013-12-17

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US08546872B2

公开(公告)日：2013-10-01

申请号：US13072366

申请日：2011-03-25

申请人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

发明人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/7881

摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

摘要翻译： 根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到 第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端 第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接， 第二和第四鳍式堆叠层结构。

公开(公告)号：US20120075928A1

公开(公告)日：2012-03-29

申请号：US13246996

申请日：2011-09-28

申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

IPC分类号： H01L29/792 ,  G11C11/34 ,  G11C11/412

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

公开(公告)号：US07749919B2

公开(公告)日：2010-07-06

申请号：US11896860

申请日：2007-09-06

申请人： Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

发明人： Kiwamu Sakuma ,  Daisuke Matsushita ,  Koichi Kato ,  Yasushi Nakasaki ,  Izumi Hirano ,  Kouichi Muraoka ,  Yuichiro Mitani ,  Shigeto Fukatsu ,  Toshihide Ito

IPC分类号： H01L21/321

CPC分类号： H01L21/28273

摘要： A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.

摘要翻译： 半导体器件包括：半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 形成在半导体衬底的一部分上的第一绝缘膜，该部分位于源区和漏区之间; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上方并由高介电常数材料制成的第二绝缘膜; 形成在所述第二绝缘膜上方的控制栅电极; 和包含具有三配位氮键的氮原子的氮化硅层，氮原子的第二最近邻原子中的至少一个为氮原子。 电荷存储膜和控制栅电极中的至少一个包含硅，氮化硅层位于第二绝缘膜和电荷存储膜和控制栅电极中的至少一个之间。

公开(公告)号：US09087715B2

公开(公告)日：2015-07-21

申请号：US13547645

申请日：2012-07-12

申请人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

发明人： Haruka Kusai ,  Kiwamu Sakuma ,  Shosuke Fujii ,  Masumi Saitoh ,  Masahiro Kiyotoshi

IPC分类号： H01L27/115 ,  H01L27/088 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/24 ,  G11C16/04 ,  H01L29/66 ,  H01L29/68 ,  H01L29/788 ,  H01L29/792 ,  G11C16/10 ,  H01L29/82

CPC分类号： H01L27/088 ,  G11C16/04 ,  G11C16/10 ,  H01L21/02367 ,  H01L21/265 ,  H01L21/32051 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/685 ,  H01L29/788 ,  H01L29/792 ,  H01L29/82

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。 结构和梁中的每一个包括沿垂直方向堆叠的半导体层。 梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

公开(公告)号：US08513725B2

公开(公告)日：2013-08-20

申请号：US13236734

申请日：2011-09-20

申请人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

发明人： Kiwamu Sakuma ,  Atsuhiro Kinoshita

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。