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    Integrated circuit, and method for transferring data
    2.
    发明授权
    Integrated circuit, and method for transferring data 有权
    集成电路和数据传输方法

    公开(公告)号：US07903480B2

    公开(公告)日：2011-03-08

    申请号：US12023592

    申请日：2008-01-31

    申请人： Konrad Seidel ,  Reinhard Ronneberger ,  Mario Wallisch

    发明人： Konrad Seidel ,  Reinhard Ronneberger ,  Mario Wallisch

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1048 ,  G11C7/12 ,  G11C16/24 ,  G11C19/00

    摘要： An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based on a capacitive coupling.

    摘要翻译： 提供了一种用于传送数据的集成电路和方法。 一个实施例提供了一种用于在集成电路中传送数据的方法。 该方法包括根据要传送的数据来驱动第一行。 基于电容耦合，数据从第一行传输到第二行。

    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS
    3.
    发明申请
    SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY COMPRISING A PLURALITY OF MEMORY CELLS 有权
    用于操作包含大量存储器单元的半导体存储器的半导体存储器和方法

    公开(公告)号：US20070076462A1

    公开(公告)日：2007-04-05

    申请号：US11240659

    申请日：2005-09-30

    申请人： Detlev Richter ,  Konrad Seidel

    发明人： Detlev Richter ,  Konrad Seidel

    IPC分类号： G11C17/00

    CPC分类号： G11C16/3418

    摘要： A method for operating a semiconductor memory (M) comprising a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), comprising the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

    摘要翻译： 一种用于操作包括多个存储单元（MC）的半导体存储器（M）的方法，其中所述存储单元（MC）彼此相邻布置，所述布置从第一存储单元（MF）开始并以最后一个结束 存储单元（ML），每个存储单元（MC）具有第一侧（S）和第二侧（D），存储单元（MC）通过位线（S）的第一侧（S）上的位线 存储单元并且通过存储单元的第二侧（D）上的另一位线（BL）连接，存储单元的第一侧（S）连接到与第一侧（D）相同的位线（BL） 每个存储单元（MC）通过相同的字线（WL）连接，包括以下步骤：选择用于操作的存储单元（MC），将第一电位（VS）应用于所有位线（BL ）连接到被布置到存储器单元的第一侧（S）的存储器单元（MC），向连接到布置到存储器单元（MC）的存储器单元（MC）的所有位线施加第二电位（VD） 存储单元的第二侧（D），并对存储单元（MC）执行所需的操作。

    Method for programming a block of memory cells, non-volatile memory device and memory card device
    4.
    发明授权
    Method for programming a block of memory cells, non-volatile memory device and memory card device 失效
    用于编程存储器单元，非易失性存储器件和存储卡器件的块的方法

    公开(公告)号：US07564718B2

    公开(公告)日：2009-07-21

    申请号：US11402649

    申请日：2006-04-12

    申请人： Konrad Seidel ,  Uwe Augustin

    发明人： Konrad Seidel ,  Uwe Augustin

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/3459 ,  G11C16/3454

    摘要： A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected for each one of the memory cells of the first group only. The first group of memory cells is verified by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

    摘要翻译： 提供了一种用于对非易失性存储器件的存储器单元的块进行编程的方法。 选择存储器单元块的第一组存储单元。 至少一个编程脉冲被编程到第一组的所有存储单元中。 仅针对第一组的每个存储器单元检测阈值电平。 通过将检测到的阈值水平中的每一个与为第一组存储器单元中的每一个提供的预定义的目标水平进行比较来验证第一组存储器单元。

    Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells
    5.
    发明授权
    Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells 有权
    用于操作包括多个存储单元的半导体存储器的半导体存储器和方法

    公开(公告)号：US07190605B1

    公开(公告)日：2007-03-13

    申请号：US11240659

    申请日：2005-09-30

    申请人： Detlev Richter ,  Konrad Seidel

    发明人： Detlev Richter ,  Konrad Seidel

    IPC分类号： G11C17/00

    CPC分类号： G11C16/3418

    摘要： A method for operating a semiconductor memory (M) including a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory cell (MC) has a first side (S) and a second side (D), the memory cells (MC) are connected by a bitline (BL) on the first side (S) of the memory cell and connected by another bitline (BL) on the second side (D) of the memory cell, the first side (S) of a memory cell is connected to a same bitline (BL) as the second side (D) of an adjacent memory cell, each of the memory cells (MC) is connected by a same wordline (WL), including the steps of: selecting a memory cell (MC) for operation, applying a first potential (VS) to all the bitlines (BL) connected to memory cells (MC) arranged to the first side (S) of the memory cell, applying a second potential (VD) to all the bitlines (BL) connected to memory cells (MC) arranged to the second side (D) of the memory cell, and performing the desired operation on the memory cell (MC).

    摘要翻译： 一种用于操作包括多个存储单元（MC）的半导体存储器（M）的方法，其中所述存储单元（MC）彼此相邻布置，所述布置从第一存储单元（MF）开始并以最后一个结束 存储单元（ML），每个存储单元（MC）具有第一侧（S）和第二侧（D），存储单元（MC）通过位线（S）的第一侧（S）上的位线 存储单元并且通过存储单元的第二侧（D）上的另一位线（BL）连接，存储单元的第一侧（S）连接到与第一侧（D）相同的位线（BL） 每个存储器单元（MC）由相同的字线（WL）连接，包括以下步骤：选择用于操作的存储单元（MC），向所有位线（BL）施加第一电位（VS） ）连接到被布置到存储器单元的第一侧（S）的存储器单元（MC），对连接到布置在存储单元（MC）的存储单元（MC）的所有位线施加第二电位（VD） （D），并且对存储单元（MC）执行所需的操作。

    Memory device and method for operating a memory device
    7.
    发明授权
    Memory device and method for operating a memory device 有权
    用于操作存储器件的存储器件和方法

    公开(公告)号：US07342829B2

    公开(公告)日：2008-03-11

    申请号：US11241817

    申请日：2005-09-30

    申请人： Gert Koebernick ,  Konrad Seidel ,  Uwe Augustin

    发明人： Gert Koebernick ,  Konrad Seidel ,  Uwe Augustin

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/0491 ,  G11C16/10 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n) within the memory area (5). The memory cells (4) are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (3). The memory device (1) is constructed such that for programming of a memory cell (4) an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line (3) to which the memory cell (4) is connected.

    摘要翻译： 存储器件（1）包括存储器阵列（2）。 存储器阵列（2）具有包括连接到导线（3）的多个导线（3）和多个存储单元（4）的至少一个存储区域（5）。 导线（3）布置在存储区域（5）内的位置（n）处。 存储单元（4）是可擦除的并且可通过施加经由相应的导线（3）提供的电编​​程脉冲（P）来编程。 存储器件（1）被构造成使得对于存储器单元（4）的编程，施加电编程脉冲（P），该编程脉冲（P）根据相应导线的位置（n）具有编程脉冲轮廓（PP） 3）连接存储单元（4）。

    Nonvolatile semiconductor memory device and method for testing the same
    8.
    发明申请
    Nonvolatile semiconductor memory device and method for testing the same 审中-公开
    非易失性半导体存储器件及其测试方法

    公开(公告)号：US20070230261A1

    公开(公告)日：2007-10-04

    申请号：US11396928

    申请日：2006-04-04

    申请人： Juerg Haufe ,  Konrad Seidel

    发明人： Juerg Haufe ,  Konrad Seidel

    IPC分类号： G11C11/34 ,  G11C7/00 ,  G11C29/00 ,  G11C16/04

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5002 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

    摘要： A nonvolatile semiconductor memory device includes transistor-based memory cells. Each memory cell has a first and a second source/drain region, a channel region separating the first and the second source/drain region, a storage layer and a control gate. The control gates of the memory cells are connected to word lines. The first and second source/drain regions are connected to bit lines respectively. Each memory cell may be programmed by injecting first charge carriers of a first polarity and may be erased by injecting second charge carriers having the opposite polarity into the storage layer respectively. By applying a high stress voltage between bit line and word line, weak insulator structures may break through such that they become detectable as short-circuits by a low voltage leakage test. By applying the stress voltage contemporaneously on both sides of the memory cells, an early overerase/overprogram, resulting from hot carrier injection, is avoided.

    摘要翻译： 非易失性半导体存储器件包括基于晶体管的存储单元。 每个存储单元具有第一和第二源极/漏极区域，分隔第一和第二源极/漏极区域的沟道区域，存储层和控制栅极。 存储单元的控制栅极连接到字线。 第一和第二源/漏区分别连接到位线。 可以通过注入第一极性的第一电荷载流子来对每个存储单元进行编程，并且可以通过将具有相反极性的第二电荷载体分别注入到存储层中来擦除。 通过在位线和字线之间施加高应力电压，弱绝缘体结构可能突破，使得它们通过低电压泄漏测试成为短路检测。 通过将应力电压同时施加在记忆细胞的两侧，避免了由热载体注入引起的早期过度/过度程序。

    Memory device and method for operating a memory device
    9.
    发明申请
    Memory device and method for operating a memory device 有权
    用于操作存储器件的存储器件和方法

    公开(公告)号：US20070076464A1

    公开(公告)日：2007-04-05

    申请号：US11241817

    申请日：2005-09-30

    申请人： Gert Koebernick ,  Konrad Seidel ,  Uwe Augustin

    发明人： Gert Koebernick ,  Konrad Seidel ,  Uwe Augustin

    IPC分类号： G11C17/00

    CPC分类号： G11C16/0475 ,  G11C16/04 ,  G11C16/0491 ,  G11C16/10 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    摘要： A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n) within the memory area (5). The memory cells (4) are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (3). The memory device (1) is constructed such that for programming of a memory cell (4) an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line (3) to which the memory cell (4) is connected.

    摘要翻译： 存储器件（1）包括存储器阵列（2）。 存储器阵列（2）具有包括连接到导线（3）的多个导线（3）和多个存储单元（4）的至少一个存储区域（5）。 导线（3）布置在存储区域（5）内的位置（n）处。 存储单元（4）是可擦除的并且可通过施加经由相应的导线（3）提供的电编​​程脉冲（P）来编程。 存储器件（1）被构造成使得对于存储器单元（4）的编程，施加电编程脉冲（P），该编程脉冲（P）根据相应导线的位置（n）具有编程脉冲轮廓（PP） 3）连接存储单元（4）。

    Memory device with adaptive sense unit and method of reading a cell array
    10.
    发明授权
    Memory device with adaptive sense unit and method of reading a cell array 有权
    具有自适应感测单元的存储器件和读取单元阵列的方法

    公开(公告)号：US07489563B2

    公开(公告)日：2009-02-10

    申请号：US11668753

    申请日：2007-01-30

    申请人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    发明人： Detlev Richter ,  Mirko Reissmann ,  Volker Zipprich-Rasch ,  Gert Köbernik ,  Uwe Augustin ,  Konrad Seidel ,  Andreas Kux ,  Hans Heitzer ,  Daniel-André Löhr ,  Sören Irmer

    IPC分类号： G11C7/00

    CPC分类号： G11C16/10 ,  G11C16/26

    摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

    摘要翻译： 提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。 平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。 通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。 通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而 增强存储设备的可靠性。