公开(公告)号：US20050162964A1

公开(公告)日：2005-07-28

申请号：US11015391

申请日：2004-12-16

申请人： Kye-Hyun Kyung ,  Kyu-Han Han

发明人： Kye-Hyun Kyung ,  Kyu-Han Han

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/4087 ,  G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C2211/4067

摘要： A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

摘要翻译： 动态半导体存储器件包括存储单元阵列，其包括连接在多个字线和多个位线对之间的多个存储单元。 模式设置部分接收从外部部分施加的模式设置代码，以响应于模式设置命令产生用于功率节省模式的功率节省模式控制信号。 在正常模式操作期间，地址控制部分对从外部施加的地址或刷新地址进行解码以选择多个字线中的一个。 地址控制部分还在省电操作模式期间选择地址的预定数量的位。 因此，半导体存储器件延长刷新周期，同时减少刷新时间，导致更低的功耗。

公开(公告)号：US07167407B2

公开(公告)日：2007-01-23

申请号：US11015391

申请日：2004-12-16

申请人： Kye-Hyun Kyung ,  Kyu-Han Han

发明人： Kye-Hyun Kyung ,  Kyu-Han Han

IPC分类号： G11C7/00

CPC分类号： G11C11/4087 ,  G11C8/08 ,  G11C8/18 ,  G11C11/406 ,  G11C2211/4067

摘要： A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

摘要翻译： 动态半导体存储器件包括存储单元阵列，其包括连接在多个字线和多个位线对之间的多个存储单元。 模式设置部分接收从外部部分施加的模式设置代码，以响应于模式设置命令产生用于功率节省模式的功率节省模式控制信号。 在正常模式操作期间，地址控制部分对从外部施加的地址或刷新地址进行解码以选择多个字线中的一个。 地址控制部分还在省电操作模式期间选择地址的预定数量的位。 因此，半导体存储器件延长刷新周期，同时减少刷新时间，导致更低的功耗。

公开(公告)号：USRE37753E1

公开(公告)日：2002-06-18

申请号：US09726665

申请日：2000-11-29

申请人： Kye-Hyun Kyung

发明人： Kye-Hyun Kyung

IPC分类号： G11C800

CPC分类号： G11C7/1093 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22

摘要： A semiconductor memory device includes input/output circuitry capable of operating in sync with an externally provided I/O clock signal. A data in buffer and a data out buffer provide for serial to parallel conversion of write data and, conversely, parallel to serial conversion of read data. The data buffers can be synchronized with the external I/O clock signal thereby decoupling their operation from the internal system clock signal. This strategy improves I/O bandwidth and further provides for matching different numbers of bit lines or word sizes as between the I/O data port and the memory array itself. An internal I/O clock generator can be provided for generating I/O clock signals, again without the limitation of synchronizing to the internal system clock signal.

摘要翻译： 半导体存储器件包括能够与外部提供的I / O时钟信号同步操作的输入/输出电路。 缓冲器和数据输出缓冲器中的数据提供写入数据的串行到并行转换，相反地，并行读取数据的串行转换。 数据缓冲器可以与外部I / O时钟信号同步，从而将其操作与内部系统时钟信号分离。 该策略提高了I / O带宽，并进一步提供了在I / O数据端口和存储器阵列本身之间匹配不同数量的位线或字体大小。 可以提供内部I / O时钟发生器，用于产生I / O时钟信号，而不受与内部系统时钟信号同步的限制。

公开(公告)号：USRE44618E1

公开(公告)日：2013-12-03

申请号：US13403738

申请日：2012-02-23

申请人： Kye-Hyun Kyung

发明人： Kye-Hyun Kyung

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

公开(公告)号：US07961018B2

公开(公告)日：2011-06-14

申请号：US12588571

申请日：2009-10-20

申请人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

发明人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

摘要翻译： 一种延迟锁定环路，适于延迟外部时钟信号并输出​​内部时钟信号，所述延迟锁定环路包括更新信号发生器，所述更新信号发生器输出被选择性地激活和去激活的更新信号，所述更新信号在所述更新信号 被激活，并且当更新信号被去激活时不活动，复制路径延迟内部时钟信号延迟半导体器件的正常路径的延迟时间，以在更新信号被激活时输出复制内部时钟信号;控制信号发生器 适于改变并根据外部和复制内部时钟信号之间的相位差输出延迟控制信号，以及可变延迟电路，其适于将外部时钟信号延迟与延迟控制信号相对应的时间，并输出 内部时钟信号。

公开(公告)号：US07894260B2

公开(公告)日：2011-02-22

申请号：US12195516

申请日：2008-08-21

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US07765442B2

公开(公告)日：2010-07-27

申请号：US11834502

申请日：2007-08-06

申请人： Kye-Hyun Kyung

发明人： Kye-Hyun Kyung

IPC分类号： G11C29/00

CPC分类号： G11C29/54 ,  G11C11/401 ,  G11C29/08 ,  G11C29/1201 ,  G11C2029/3602 ,  G11C2029/4002

摘要： Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

摘要翻译： 本发明的示例性实施例包括不使用数据和无数据测试方法可测试的存储器件。 存储器件包括多个用于存储测试图案的寄存器，寄存器耦合到输入/输出DQ焊盘。 当设置存储器件的模式寄存器时，测试模式存储在寄存器中。 存储器件响应于写测试信号将测试图形传送到DQ垫，并且响应于读取测试信号将测试图案从DQ垫传送到数据输入缓冲器。 存储器件将传送到数据输入缓冲器的测试图形写入存储单元。 存储器件响应于写入测试信号读取存储在存储器单元中的数据，并且响应读取的测试信号将存储单元数据从DQ焊盘传送到比较器。 存储器装置将测试模式与传送到比较器的存储单元数据进行比较，并产生指示信号以指示比较结果。

公开(公告)号：US07426145B2

公开(公告)日：2008-09-16

申请号：US11802443

申请日：2007-05-23

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US20060171225A1

公开(公告)日：2006-08-03

申请号：US11327877

申请日：2006-01-09

申请人： Hye-In Chol ,  Kye-Hyun Kyung

发明人： Hye-In Chol ,  Kye-Hyun Kyung

IPC分类号： G11C7/02

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/065

摘要： A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of data from a memory cell to the local input/output line and the control circuit may be configured to disable transfer of data via the column select gate responsive to the global input/output line sense amplifier enable signal.

摘要翻译： 存储器件包括控制电路，其被配置为响应于全局输入/输出线路读出放大器使能信号禁用本地输入/输出线路读出放大器。 该设备还可以包括配置为控制从存储器单元向本地输入/输出线路传输数据的列选择栅极，并且控制电路可被配置为响应于全局输入/输出而经由列选择门禁止数据传输 线路感测放大器使能信号。

公开(公告)号：US20060146616A1

公开(公告)日：2006-07-06

申请号：US11325102

申请日：2006-01-04

申请人： Nak-Won Heo ,  Kye-Hyun Kyung

发明人： Nak-Won Heo ,  Kye-Hyun Kyung

IPC分类号： G11C5/14

CPC分类号： G11C11/406 ,  G11C8/08 ,  G11C11/4085 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.

摘要翻译： 一种半导体存储器件，包括连接到字线和字线电压发生器的存储单元。 字线电压发生器在备用状态下向字线提供第一负电压，并且在刷新操作中将相对于地面的第一负电压相对于第一负电压提供给字线。 因此，抑制了通过栅极引起的漏极泄漏（GIDL）在存储单元的晶体管处产生的漏电流，以提高刷新操作的性能。