Abstract:
An embodiment provides a semiconductor element, which comprises: a substrate; and a semiconductor structure disposed on the substrate, wherein the semiconductor structure comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and a light absorption layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and the light absorption layer has a value of 1.2 to 1.5 as a ratio of a maximum outer periphery length of an upper surface thereof with respect to a maximum area of the upper surface thereof.
Abstract:
A light emitting device having an enhanced surface property and an electrical property is provided. The light emitting device includes a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode disposed on one side of the light emitting structure and electrically connected to the first semiconductor layer, a second electrode disposed on one side of the light emitting structure and electrically connected to the second semiconductor layer, and an ohmic contact including a first layer disposed between the second electrode and the second semiconductor layer and having aluminum (Al), a second layer including at least one MxAly alloy formed by a reaction with Al included in the first layer, and a third layer disposed on the second layer and having gold (Au) is provided.
Abstract:
Embodiments provide a light emitting device including a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a sub-mount, first and second metal pads disposed on the sub-mount and electrically spaced apart from one another, a one first bump disposed between the first conductive semiconductor layer and the first metal pad and a second bump located between the second conductive semiconductor layer and the second metal pad. A plurality of active areas in which The first semiconductor layer and the active layer are disposed are spaced apart from one another when viewed in plan.