Abstract:
An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer.
Abstract:
An electronic shelf label system is provided. There is provided a method in which an electronic shelf label periodically transmits its remaining battery capacity to a server in a electronic shelf label system according to the present invention, and the server converts the battery level into a remaining battery life (time) and provides the same, so that a manager can check the remaining battery life in a management mode of the server and a terminal, and easily manage an electronic shelf label using a battery.
Abstract:
Disclosed is an epitaxial wafer including a substrate and an epitaxial structure disposed on the substrate, wherein the epitaxial structure is doped with an n-type or p-type dopant and has a doping uniformity of 10% or less.
Abstract:
A pressure detecting sensor according to an embodiment of the present invention comprises: a first electrode layer including a plurality of signal electrodes arranged in a first region and a plurality of wiring electrodes arranged in a second region and connected to the plurality of signal electrodes, the first electrode layer being made of a conductive fiber; an elastic dielectric layer arranged in the first region; and a second electrode layer arranged in the elastic dielectric layer, the second electrode layer being made of a conductive fiber.
Abstract:
Disclosed are a phosphor composition and a light emitting apparatus including the same. The phosphor composition has a compositional formula of AzCxO12:RE, wherein the z is 0≤z≤3, the x is 0≤x≤5, the A includes at least one selected from the group consisting of Y, Sc, Gd and Lu, the C includes at least one selected from the group consisting of B, Al and Ga, and the RE includes at least one selected from the group consisting of Eu, Ce, Sm, Yb, Dy, Gd, Tm and Lu. The light emitting apparatus includes the phosphor composition.
Abstract:
Disclosed are a phosphor and a light emitting device having the same. The light emitting device includes a light emitting chip, a plurality of phosphors to absorb a portion of light emitted from the light emitting chip and to emit lights having mutually different peak wavelengths, and a molding member provided on the light emitting chip and including the phosphors. The phosphors include a first phosphor to emit light having a first peak wavelength, a second phosphor to absorb the portion of the light emitted from the light emitting chip and to emit light having a second peak wavelength, and a third phosphor to absorb the portion of the light emitted from the light emitting chip and to emit light having a third peak wavelength. The first to third peak wavelengths have mutually different color spectrums, and a light emission spectrum in which the first to third peak wavelengths are mixed with each other has a luminous intensity having a substantially flat section in at least 30 nm at a peak wavelength thereof.
Abstract:
An epitaxial wafer includes an epitaxial layer disposed on a substrate. The epitaxial layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on the first semiconductor layer and having a thickness that is thicker than that of the first semiconductor layer. A surface defect density of the second semiconductor layer is 0.1/cm2 or less.
Abstract translation:外延晶片包括设置在基板上的外延层。 外延层包括设置在基板上的第一半导体层和设置在第一半导体层上并具有比第一半导体层厚的厚度的第二半导体层。 第二半导体层的表面缺陷密度为0.1 / cm 2以下。
Abstract:
Disclosed is an etching treatment apparatus. The etching treatment apparatus includes a crucible to receive a wafer, a wafer jig part having a groove into which the wafer is seated, and a size adjusting part inserted into the groove while making contact with the edge of the wafer.