公开(公告)号：US20230182443A1

公开(公告)日：2023-06-15

申请号：US18076544

申请日：2022-12-07

Applicant: LG INNOTEK CO., LTD.

Inventor： Koh Eun Lee ,  Han Sang Kim ,  Min Young Hwang

IPC: B32B15/09 ,  B32B15/20 ,  B32B27/20 ,  C08L67/00 ,  H05K1/03 ,  C08K7/14

CPC classification number: B32B15/09 ,  B32B15/20 ,  B32B27/20 ,  C08L67/00 ,  H05K1/0366 ,  C08K7/14 ,  B32B2262/101 ,  B32B2457/14 ,  C08L2205/12 ,  B32B2307/204 ,  B32B2305/55 ,  B32B2305/22 ,  B32B2307/308

Abstract: A resin composition for a semiconductor package according to an embodiment includes a resin composition comprising a resin and a filler provided in the resin, wherein the resin includes a soluble liquid crystal polymer resin, and wherein the filler has a negative coefficient of thermal expansion (negative CTE) and is provided in the soluble liquid crystal polymer resin.

公开(公告)号：US09559031B2

公开(公告)日：2017-01-31

申请号：US14354058

申请日：2012-10-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Min Young Hwang

IPC: H01L21/8238 ,  H01L23/31 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L23/3171 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02667 ,  H01L29/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an epi wafer according to the embodiment comprises depositing an epi layer on a wafer in a first chamber; transferring the wafer to a second chamber connected to the first chamber; forming a protective layer on the wafer in the second chamber; and cooling the wafer in the second chamber.Further, an apparatus for fabricating an epi wafer according to the embodiment comprises a first chamber comprising an epi deposition part; a second chamber comprising a protective layer forming part and a cooling part; and a wafer transfer apparatus connected to lower portions of the first chamber and the second chamber.

Abstract translation: 此外，根据实施例的用于制造外延晶片的装置包括：第一室，包括外延沉积部分; 第二室，包括保护层形成部分和冷却部分; 以及连接到第一室和第二室的下部的晶片传送装置。

公开(公告)号：US12048095B2

公开(公告)日：2024-07-23

申请号：US17430708

申请日：2020-02-10

Applicant: LG INNOTEK CO., LTD.

Inventor： Min Young Hwang ,  Moo Seong Kim ,  Byeong Kyun Choi

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/113 ,  H05K1/0207 ,  H05K1/0296 ,  H05K2201/096

Abstract: A circuit board according to one embodiment comprises a first insulation layer, a circuit pattern on the first insulation layer, and a second insulation layer on the circuit pattern, wherein a heat transfer member is arranged inside the first insulation layer and/or the second insulation layer, and the heat transfer member is arranged while coming in contact with a side surface of the insulation layer.

公开(公告)号：US09793355B2

公开(公告)日：2017-10-17

申请号：US14648704

申请日：2013-11-21

Applicant: LG INNOTEK CO., LTD.

Inventor： Seok Min Kang ,  Ji Hye Kim ,  Min Young Hwang

IPC: H01L29/16 ,  H01L29/36 ,  H01L29/872 ,  H01L33/22 ,  H01L33/26 ,  H01L33/34 ,  H01L21/02 ,  H01L33/02 ,  H01L29/24 ,  H01L29/34 ,  H01L33/00

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02521 ,  H01L21/02529 ,  H01L29/0878 ,  H01L29/24 ,  H01L29/34 ,  H01L29/36 ,  H01L29/7802 ,  H01L29/872 ,  H01L33/0033 ,  H01L33/025 ,  H01L33/22 ,  H01L33/26 ,  H01L33/34

Abstract: An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer.

公开(公告)号：US11974388B2

公开(公告)日：2024-04-30

申请号：US17310657

申请日：2020-02-13

Applicant: LG INNOTEK CO., LTD.

Inventor： Byeong Kyun Choi ,  Min Young Hwang ,  Hyun Gu Im

IPC: H05K1/03 ,  H05K1/02

CPC classification number: H05K1/0237 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/036 ,  H05K2201/09481

Abstract: A circuit board, according to an embodiment, comprises: a first insulating layer; a second insulating layer disposed on one surface of the first insulating layer; and a third insulating layer disposed on the other surface of the first insulating layer. A circuit pattern is disposed on at least one insulating layer from among the first to third insulating layers, at least one insulating layer from among the first to third insulating layers comprises glass fiber, at least one insulating layer from among the first to third insulating layers does not comprise glass fiber, and the thicknesses of the first to third insulating layers are different from each other.

公开(公告)号：US12016128B2

公开(公告)日：2024-06-18

申请号：US17462157

申请日：2021-08-31

Applicant: LG INNOTEK CO., LTD.

Inventor： Min Young Hwang ,  Byeong Kyun Choi ,  Jin Seok Lee ,  Moo Seong Kim

IPC: H05K3/10 ,  H05K1/09

CPC classification number: H05K3/10 ,  H05K1/09 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/0959 ,  H05K2203/0723

Abstract: A circuit board according to an embodiment includes an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes a copper foil layer disposed on the insulating layer, a first plating layer disposed on the copper foil layer, and a second plating layer disposed on the first plating layer, and wherein the copper foil layer has a thickness in a range of 2 μm to 5 μm.

公开(公告)号：US20140319544A1

公开(公告)日：2014-10-30

申请号：US14354058

申请日：2012-10-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Min Young Hwang

IPC: H01L23/31 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L23/3171 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02667 ,  H01L29/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an epi wafer according to the embodiment comprises depositing an epi layer on a wafer in a first chamber; transferring the wafer to a second chamber connected to the first chamber; forming a protective layer on the wafer in the second chamber; and cooling the wafer in the second chamber.Further, an apparatus for fabricating an epi wafer according to the embodiment comprises a first chamber comprising an epi deposition part; a second chamber comprising a protective layer forming part and a cooling part; and a wafer transfer apparatus connected to lower portions of the first chamber and the second chamber.

Abstract translation: 根据实施例的用于制造外延晶片的方法包括在第一室中的晶片上沉积外延层; 将晶片转移到连接到第一室的第二室; 在所述第二室中在所述晶片上形成保护层; 并在第二室中冷却晶片。 此外，根据实施例的用于制造外延晶片的装置包括：第一室，包括外延沉积部分; 第二室，包括保护层形成部分和冷却部分; 以及连接到第一室和第二室的下部的晶片传送装置。