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13 条记录 (耗时 0.014 秒)

    Integrated circuit having reduced clock cross-talk
    1.
    发明授权
    Integrated circuit having reduced clock cross-talk 失效
    集成电路具有减少的时钟串扰

    公开(公告)号：US4707844A

    公开(公告)日：1987-11-17

    申请号：US875806

    申请日：1986-06-18

    申请人： Hendrikus J. M. Veendrick ,  Adrianus T. Van Zanten ,  Leonardus C. M. G. Pfennings

    发明人： Hendrikus J. M. Veendrick ,  Adrianus T. Van Zanten ,  Leonardus C. M. G. Pfennings

    IPC分类号： G11C27/04 ,  G11C8/18 ,  G11C19/28 ,  H03K23/46 ,  G11C7/02

    CPC分类号： G11C19/285 ,  G11C8/18

    摘要： Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.

    摘要翻译： 电荷耦合器件由于连续电极之间的重叠而对时钟串扰非常敏感。 当时钟线通过低欧姆阻抗周期性地连接到地，这种串扰的影响减小了。 为此，每个时钟线由缓冲器控制，其输出端连接到时钟线。 钳位晶体管连接在输出和地之间。 当该钳位晶体管通过输出信号控制并且同时由缓冲器的输入信号控制时，输出在通过仅一个钳位晶体管预期串扰的时刻被钳位到地 。

    Integrated memory circuit having a block selection circuit
    2.
    发明授权
    Integrated memory circuit having a block selection circuit 失效
    具有块选择电路的集成存储电路

    公开(公告)号：US4849943A

    公开(公告)日：1989-07-18

    申请号：US77154

    申请日：1987-07-24

    申请人： Leonardus C. M. G. Pfennings

    发明人： Leonardus C. M. G. Pfennings

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401

    CPC分类号： G11C8/14 ,  G11C8/12

    摘要： Memory cells in an integrated memory circuit are arranged in blocks and selected by block selection gates. This method of activation offers the advantage that the memory cells are accessed faster and that the power consumption is lower than in a memory which is not subdivided into blocks, because only a small group of memory cells is activated per selection operation. A block selection circuit is provided in which selection gates of two neighboring rows of memory cells have one common transistor. As a result of the multiple use of contact areas and the use of a mirror-symmetrical architecture, the lay-out can make optimum use of the available substrate surface area.

    Logic boatstrapping circuit having a feedforward kicker circuit
    3.
    发明授权
    Logic boatstrapping circuit having a feedforward kicker circuit 失效
    具有前馈斩波电路的逻辑舟形电路

    公开(公告)号：US4697111A

    公开(公告)日：1987-09-29

    申请号：US698999

    申请日：1985-02-07

    申请人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings ,  Wilhelmus C. H. Gubbels

    发明人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings ,  Wilhelmus C. H. Gubbels

    IPC分类号： H03K19/094 ,  H03K17/06 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0944 ,  H03K4/58 ,  H03K17/04 ,  H03K17/10

    CPC分类号： H03K19/00315 ,  H03K19/01714 ,  H03K19/09443

    摘要： An integrated logic circuit includes a push-pull amplifier stage, in which by means of a bootstrap circuit the potential at the gate of the "push" transistor is brought above the supply voltage so that the output voltage of the amplifier lies above the supply voltage minus the threshold voltage of the push transistor. In order to prevent the charge from leaking away after the bootstrap capacitance has been charged via an enhancement transistor, the enhancement transistor is cut off by means of the "low" input signal. A second bootstrap circuit (between the input and the gate of the enhancement transistor) ensures that the first bootstrap capacitance is charged up to the full supply voltage because the latter gate electrode is lifted above the supply voltage by the second bootstrap.

    摘要翻译： 集成逻辑电路包括一个推挽放大器级，其中通过自举电路使“推”晶体管的栅极处的电位高于电源电压，使得放大器的输出电压高于电源电压 减去推式晶体管的阈值电压。 为了防止在自举电容经由增强型晶体管充电之后电荷泄漏，增强晶体管通过“低”输入信号被切断。 第二自举电路（在增强晶体管的输入和栅极之间）确保第一自举电容被充电至全电源电压，因为后一栅电极被第二自举提升到电源电压以上。

    Digital integrated circuit comprising complementary field effect transistors
    4.
    发明授权
    Digital integrated circuit comprising complementary field effect transistors 失效
    包括互补场效应晶体管的数字集成电路

    公开(公告)号：US4667303A

    公开(公告)日：1987-05-19

    申请号：US600051

    申请日：1984-04-13

    申请人： Leonardus C. M. G. Pfennings

    发明人： Leonardus C. M. G. Pfennings

    IPC分类号： H03K19/017 ,  H03K3/356 ,  H03K5/02 ,  H03K17/687 ,  H03K19/01 ,  H03K19/0948 ,  G06F7/50

    CPC分类号： H03K3/356104

    摘要： Digital integrated C-MOS circuit in which two cross-coupled P-MOS transistors are connected by two separation transistors (N-MOS) to two complementary switching N-MOS transistor logic networks. The gate electrodes of the separation transistor are connected to a reference voltage source. The switching speed of the C-MOS circuit is increased in that (a) the voltage sweep across the logic networks is reduced; (b) each P-MOS transistor, which is connected by a separation transistor to a junction of the logic network to be charged, is slightly conducting and so is "ready" to charge such junction, and (c) the separation transistor between the fully conducting P-MOS transistor and the junction to be discharged in the second logic network constitutes a high impedance which prevents the conducting P-MOS transistor from charging that junction.

    摘要翻译： 数字集成C-MOS电路，其中两个交叉耦合的P-MOS晶体管通过两个分离晶体管（N-MOS）连接到两个互补开关N-MOS晶体管逻辑网络。 分离晶体管的栅电极连接到参考电压源。 C-MOS电路的切换速度增加，因为（a）跨越逻辑网络的电压扫描减少; （b）通过分离晶体管连接到要充电的逻辑网络的结点的每个P-MOS晶体管是稍微导通的，并且“准备”为这种结点充电，以及（c）分离晶体管在 完全导电的P-MOS晶体管，并且在第二逻辑网络中放电的结构成高阻抗，防止导电P-MOS晶体管对该结进行充电。

    Integrated memory circuit having complementary bit line charging
    6.
    发明授权
    Integrated memory circuit having complementary bit line charging 失效
    具有互补位线充电的集成存储电路

    公开(公告)号：US4823319A

    公开(公告)日：1989-04-18

    申请号：US39400

    申请日：1987-04-17

    申请人： Leonardus C. M. G. Pfennings

    发明人： Leonardus C. M. G. Pfennings

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C7/1078 ,  G11C11/419 ,  G11C7/18

    摘要： In a memory cell which is connected between two bit lines, information is stored after selection by causing a first bit line to convey a signal which is complementary to that on a second bit line. It is known, starting from a single data supply line which may convey either a high or a low signal, to provide a memory circuit per column with inverting means so as to be able to charge both bit lines complementarily. Here, this complementary charging is done by connecting, upon selection, the first bit line to the data supply line and connecting a transistor with its main electrodes between ground and the second bit line, which transistor receives the data at its control electrode. This transistor then constitutes, with the bit line load, an inverter. Lay-out aspects relate to the common use of substrate area of two adjacent columns and the common use of a contact in the shown circuit arrangement.

    Circuit arrangement for a dual bus line
    8.
    发明授权
    Circuit arrangement for a dual bus line 失效
    双总线线路布置

    公开(公告)号：US4931667A

    公开(公告)日：1990-06-05

    申请号：US266172

    申请日：1988-11-02

    申请人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

    发明人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

    IPC分类号： G06F3/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/41 ,  G11C11/419

    CPC分类号： G11C7/1048

    摘要： Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

    摘要翻译： 通过由差分放大器评估的差分信号经由双总线传输数据，特别是出于防止干扰的原因。 然而，这种差分放大器仅具有有限的输入电压范围，或其中不能操作的输入信号的死电压范围。 为了防止两条总线上的电压进入该死区，由于总线上的共模干扰信号或由于差分放大器的馈电电压的电压下降，两条总线被连接 根据本发明，调整电路使得两个总线的电压在死电压范围之外的方向上改变相同的量。 这可以防止差分放大器的未指定条件，而不会明显影响两条总线上的差分信号。 描述了集成存储器的应用。