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12 条记录 (耗时 0.027 秒)

    Logic boatstrapping circuit having a feedforward kicker circuit
    1.
    发明授权
    Logic boatstrapping circuit having a feedforward kicker circuit 失效
    具有前馈斩波电路的逻辑舟形电路

    公开(公告)号：US4697111A

    公开(公告)日：1987-09-29

    申请号：US698999

    申请日：1985-02-07

    申请人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings ,  Wilhelmus C. H. Gubbels

    发明人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings ,  Wilhelmus C. H. Gubbels

    IPC分类号： H03K19/094 ,  H03K17/06 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0944 ,  H03K4/58 ,  H03K17/04 ,  H03K17/10

    CPC分类号： H03K19/00315 ,  H03K19/01714 ,  H03K19/09443

    摘要： An integrated logic circuit includes a push-pull amplifier stage, in which by means of a bootstrap circuit the potential at the gate of the "push" transistor is brought above the supply voltage so that the output voltage of the amplifier lies above the supply voltage minus the threshold voltage of the push transistor. In order to prevent the charge from leaking away after the bootstrap capacitance has been charged via an enhancement transistor, the enhancement transistor is cut off by means of the "low" input signal. A second bootstrap circuit (between the input and the gate of the enhancement transistor) ensures that the first bootstrap capacitance is charged up to the full supply voltage because the latter gate electrode is lifted above the supply voltage by the second bootstrap.

    摘要翻译： 集成逻辑电路包括一个推挽放大器级，其中通过自举电路使“推”晶体管的栅极处的电位高于电源电压，使得放大器的输出电压高于电源电压 减去推式晶体管的阈值电压。 为了防止在自举电容经由增强型晶体管充电之后电荷泄漏，增强晶体管通过“低”输入信号被切断。 第二自举电路（在增强晶体管的输入和栅极之间）确保第一自举电容被充电至全电源电压，因为后一栅电极被第二自举提升到电源电压以上。

    Integrated circuit having reduced clock cross-talk
    2.
    发明授权
    Integrated circuit having reduced clock cross-talk 失效
    集成电路具有减少的时钟串扰

    公开(公告)号：US4707844A

    公开(公告)日：1987-11-17

    申请号：US875806

    申请日：1986-06-18

    申请人： Hendrikus J. M. Veendrick ,  Adrianus T. Van Zanten ,  Leonardus C. M. G. Pfennings

    发明人： Hendrikus J. M. Veendrick ,  Adrianus T. Van Zanten ,  Leonardus C. M. G. Pfennings

    IPC分类号： G11C27/04 ,  G11C8/18 ,  G11C19/28 ,  H03K23/46 ,  G11C7/02

    CPC分类号： G11C19/285 ,  G11C8/18

    摘要： Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.

    摘要翻译： 电荷耦合器件由于连续电极之间的重叠而对时钟串扰非常敏感。 当时钟线通过低欧姆阻抗周期性地连接到地，这种串扰的影响减小了。 为此，每个时钟线由缓冲器控制，其输出端连接到时钟线。 钳位晶体管连接在输出和地之间。 当该钳位晶体管通过输出信号控制并且同时由缓冲器的输入信号控制时，输出在通过仅一个钳位晶体管预期串扰的时刻被钳位到地 。

    Logic circuits with data resynchronization
    4.
    发明授权
    Logic circuits with data resynchronization 失效
    具有数据重新同步的逻辑电路

    公开(公告)号：US4918331A

    公开(公告)日：1990-04-17

    申请号：US358478

    申请日：1989-05-26

    申请人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings

    发明人： Adrianus T. Van Zanten ,  Hendrikus J. M. Veendrick ,  Leonardus C. M. G. Pfennings

    IPC分类号： H03K3/037 ,  H03K19/003

    CPC分类号： H03K3/0372 ,  H03K19/00323

    摘要： In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.

    摘要翻译： 在相对大的（集成的）电路系统中，数据信号可以经历时钟脉冲周期的数量级的延迟。 接收电路（即接收数据信号）然后接收数据信号太晚（时钟脉冲已经停止），并且在此时刻不再接管数据信号用于进一步的处理或传输。 在根据本发明的系统中，通过延迟元件（例如，串联的反相电路）将时钟脉冲引导到接收电路（主/从触发器的从机）。 接收电路的数据输出连接到另一个电路（另一主/从触发器的主机）的数据输入端，其接收未延迟的时钟脉冲，接收电路和另一个电路之间的数据延迟可以忽略不计。 因此数据延迟分布在两个时钟脉冲上。

    Integrated CMOS gate-array circuit
    9.
    发明授权
    Integrated CMOS gate-array circuit 失效
    集成CMOS门阵列电路

    公开(公告)号：US5250823A

    公开(公告)日：1993-10-05

    申请号：US804468

    申请日：1991-12-05

    申请人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. van den Elshout ,  Dirk W. Harberts

    发明人： Hendrikus J. M. Veendrick ,  Andreas A. J. M. van den Elshout ,  Dirk W. Harberts

    IPC分类号： H01L27/118 ,  H01L27/104 ,  H01L29/76

    CPC分类号： H01L27/11807

    摘要： A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

    摘要翻译： 门阵列电路包括连续布置的n沟道晶体管和相邻的p沟道晶体管行。 两行由至少三个具有两个子晶体的窄晶体管和一个宽晶体管的子线组成，其中沟道宽度至少为窄晶体管宽度的三倍。 栅电极对于三个子线是共同的。 优选地，宽的子行布置在狭窄的子宫之间的中心。 这种结构在设计要实现的功能方面具有非常高的密度和非常高的灵活性的优点。