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    Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof
    1.
    发明授权
    Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof 失效
    自对准的平面化薄膜晶体管，采用该晶体管的器件及其制造方法

    公开(公告)号：US06818487B2

    公开(公告)日：2004-11-16

    申请号：US10631533

    申请日：2003-07-31

    申请人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

    IPC分类号： H01L2100

    CPC分类号： H01L29/66787 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78636

    摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

    摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管上方的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。

    Self-aligned, planarized thin-film transistors, devices employing the same
    2.
    发明授权
    Self-aligned, planarized thin-film transistors, devices employing the same 失效
    自对准的平面化薄膜晶体管，采用它们的器件

    公开(公告)号：US06649935B2

    公开(公告)日：2003-11-18

    申请号：US09795535

    申请日：2001-02-28

    申请人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Li-Kong Wang

    IPC分类号： H01L2976

    CPC分类号： H01L29/66787 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/78636

    摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

    摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管之上的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。

    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
    3.
    发明授权
    Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效
    用于形成这种混合取向基板的混合取向基板和晶体压印方法

    公开(公告)号：US07875960B2

    公开(公告)日：2011-01-25

    申请号：US12182560

    申请日：2008-07-30

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/04

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/045

    摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

    摘要翻译： 一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域 层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。 体硅区域各自定向为具有第三晶体取向。 还提供了形成SOI区域和体硅区域的镶嵌或印记方法。

    ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS
    4.
    发明申请
    ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS 有权
    半导体集成电路中的电子熔丝

    公开(公告)号：US20100320563A1

    公开(公告)日：2010-12-23

    申请号：US12870921

    申请日：2010-08-30

    申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Robert Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L21/76807 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

    摘要翻译： 一个结构。 该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。

    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    5.
    发明授权
    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
    将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法

    公开(公告)号：US07692250B2

    公开(公告)日：2010-04-06

    申请号：US11927110

    申请日：2007-10-29

    申请人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L27/12

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

    Method of fabricating semiconductor structures for latch-up suppression
    6.
    发明授权
    Method of fabricating semiconductor structures for latch-up suppression 失效
    制造用于闭锁抑制的半导体结构的方法

    公开(公告)号：US07648869B2

    公开(公告)日：2010-01-19

    申请号：US11330689

    申请日：2006-01-12

    申请人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Shunhua Thomas Chang ,  Toshiharu Furukawa ,  Robert J. Gauthier, Jr. ,  David Vaclav Horak ,  Charles William Koburger, III ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/0921 ,  H01L21/823878

    摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    9.
    发明授权
    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
    将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法

    公开(公告)号：US07352034B2

    公开(公告)日：2008-04-01

    申请号：US11211956

    申请日：2005-08-25

    申请人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    发明人： Roger Allen Booth, Jr. ,  Jack Allan Mandelman ,  William Robert Tonti

    IPC分类号： H01L29/94

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。