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公开(公告)号：US20100327430A1
公开(公告)日：2010-12-30
申请号：US12491517
申请日：2009-06-25
CPC分类号： H01L23/3735 , H01L2224/73204 , H01L2224/73253 , H01L2224/83951
摘要： Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE1, the buffer layer has a second CTE, CTE2, and the semiconductor device has a third CTE, CTE3, wherein CTE1>CTE2>CTE3.
摘要翻译： 公开了一种多层热界面材料，其包括金属热界面材料的第一层，缓冲层，优选为第二层热界面材料，其可以是金属或非金属的。 多层热界面材料与芯片载体衬底的半导体器件组件，用于附接到衬底的散热器，安装在衬底上的散热器和放置在散热器下方的多层热界面材料结合使用 散热器和半导体器件。 散热器具有第一热膨胀系数（CTE），CTE1，缓冲层具有第二CTE，CTE2，半导体器件具有第三个CTE CTE3，其中CTE1> CTE2> CTE3。
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2.发明授权Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging 有权通过偏移来减少微电子封装中第一级互连（FLI）下的应力公开(公告)号：US07812438B2
公开(公告)日：2010-10-12
申请号：US11970130
申请日：2008-01-07
IPC分类号： H01L23/04
CPC分类号： H01L24/12 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/13099 , H01L2224/141 , H01L2224/14104 , H01L2224/16 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.
摘要翻译： 本发明涉及一种改进的微电子器件，其通过减小施加在通孔上的拉应力来降低BEOL分层，所述通孔将第一级互连与BEOL连接。 通过将通孔移向硅芯片的中心或者将UBM转移到硅芯片的角部来减小施加在通孔上的拉伸应力。
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3.发明申请Flat Laminate, Symmetrical Test Structures and Method of Use To Gauge White Bump Sensitivity 有权扁平层压板，对称测试结构和使用方法来测量白色凹凸感光度公开(公告)号：US20130098176A1
公开(公告)日：2013-04-25
申请号：US13277246
申请日：2011-10-20
申请人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
发明人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
IPC分类号： G01N33/00
CPC分类号： H01L22/30 , B05D1/36 , G01N3/60 , G01N19/04 , G01N25/16 , G01N2203/0296 , G01N2203/0298 , H01L24/13 , H01L2224/131 , H01L2924/10253 , H01L2924/351 , H01L2924/014 , H01L2924/00
摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
摘要翻译： 公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。 测试结构包括平板层压结构。 使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。
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4.发明申请FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING 审中-公开有机硅芯片组件与有机硅片式印刷电路板公开(公告)号：US20110195543A1
公开(公告)日：2011-08-11
申请号：US13091317
申请日：2011-04-21
IPC分类号： H01L21/60
CPC分类号： H01L23/49816 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/09436 , Y02P70/613 , H01L2924/00014 , H01L2924/00
摘要： Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.
摘要翻译： 公开了使用无铅焊料的倒装芯片组装和方法的实施例。 该组件包括在有机层压基板上填充和溢出阻焊剂开口的蘑菇镀金属层。 金属层的下部为其相应的抗焊剂开口提供结构支撑。 每个金属层的上部（即盖）为集成电路器件和衬底之间的焊接点提供着陆点，从而允许增强的焊料体积控制。 额外的结构支撑与增强的焊料体积控制相结合，最大限度地减少了所得到的焊点的应变。 此外，帽还允许组件的衬底侧上的焊点的最小直径大于阻焊剂开口的直径。 因此，本发明将C4可靠性问题与层压板设计问题分开，从而允许更大的设计灵活性。
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5.发明授权公开(公告)号：US09472520B2
公开(公告)日：2016-10-18
申请号：US13590332
申请日：2012-08-21
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05666 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11901 , H01L2224/13005 , H01L2224/13013 , H01L2224/13023 , H01L2224/1308 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13655 , H01L2224/13666 , H01L2224/13671 , H01L2224/13684 , H01L2224/16235 , H01L2224/81815 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/2064 , H01L2924/351 , H01L2924/35121 , H01L2924/37001 , H01L2924/384 , Y10T156/10 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
摘要翻译： 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。
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6.发明授权Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity 有权扁平层压板，对称测试结构和测量白色凸起敏感度的方法公开(公告)号：US08957531B2
公开(公告)日：2015-02-17
申请号：US13277246
申请日：2011-10-20
申请人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
发明人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
IPC分类号： H01L23/538 , H01L21/66 , H01L23/00 , G01N3/60 , G01N19/04
CPC分类号： H01L22/30 , B05D1/36 , G01N3/60 , G01N19/04 , G01N25/16 , G01N2203/0296 , G01N2203/0298 , H01L24/13 , H01L2224/131 , H01L2924/10253 , H01L2924/351 , H01L2924/014 , H01L2924/00
摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
摘要翻译： 公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。 测试结构包括平板层压结构。 使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。
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公开(公告)号：US08794079B2
公开(公告)日：2014-08-05
申请号：US13289121
申请日：2011-11-04
申请人： Paul F. Bodenweber , Virendra R. Jadhav , Steven P. Ostrander , Kamal Sikka , Jiantao Zheng , Jeffrey A. Zitz
发明人： Paul F. Bodenweber , Virendra R. Jadhav , Steven P. Ostrander , Kamal Sikka , Jiantao Zheng , Jeffrey A. Zitz
IPC分类号： G01N3/08
CPC分类号： G01L5/0038 , G01L5/0057 , G01L5/0076 , G01N3/08 , G01N27/22 , G01N2203/0617 , G01N2203/0629 , G01N2203/0682
摘要： An apparatus for determining a magnitude of a compressive load applied to a piston including a compliant film disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the magnitude of the compressive load is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to a deformation of the compliant film as the compressive load is applied.
摘要翻译： 提供一种用于确定施加到包括设置在第一和第二元件之间的柔性膜的活塞的压缩载荷的大小的装置。 该装置包括第一部分，该第一部分沿着移动方向可移动地沿着移动方向移动，沿该运动方向确定压缩载荷的大小，第二部分，可沿着运动方向与第二部件移动;以及传感器，用于测量第一 和运动方向上的第二部分，所测量的距离与施加压缩载荷时柔顺膜的变形有关。
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公开(公告)号：US08717043B2
公开(公告)日：2014-05-06
申请号：US13191729
申请日：2011-07-27
摘要： An apparatus for determining a thickness change of thermal interface material (TIM) disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the TIM thickness is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to the TIM thickness change.
摘要翻译： 提供一种用于确定设置在第一和第二元件之间的热界面材料（TIM）的厚度变化的装置。 该装置包括：第一部件，沿第一部件可沿着移动方向移动，TIM移动方向上沿着移动方向确定TIM厚度;第二部件，其沿着移动方向与第二部件移动;以及传感器，用于测量第一部件和第二部件之间的距离 在移动方向上，测量的距离与TIM厚度变化有关。
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9.发明申请MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME 审中-公开用于减少应力互连的多层支架及其制造方法公开(公告)号：US20120312447A1
公开(公告)日：2012-12-13
申请号：US13590332
申请日：2012-08-21
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05666 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11901 , H01L2224/13005 , H01L2224/13013 , H01L2224/13023 , H01L2224/1308 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13184 , H01L2224/13655 , H01L2224/13666 , H01L2224/13671 , H01L2224/13684 , H01L2224/16235 , H01L2224/81815 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/2064 , H01L2924/351 , H01L2924/35121 , H01L2924/37001 , H01L2924/384 , Y10T156/10 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
摘要翻译： 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其构造成吸收在芯片组装和热偏移期间施加的力。
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10.发明申请VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING 有权通过微电子封装中的第一级互连（FLI）降低压力公开(公告)号：US20090174084A1
公开(公告)日：2009-07-09
申请号：US11970130
申请日：2008-01-07
IPC分类号： H01L23/488
CPC分类号： H01L24/12 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/13099 , H01L2224/141 , H01L2224/14104 , H01L2224/16 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.
摘要翻译： 本发明涉及一种改进的微电子器件，其通过减小施加在通孔上的拉应力来降低BEOL分层，所述通孔将第一级互连与BEOL连接。 通过将通孔移向硅芯片的中心或者将UBM转移到硅芯片的角部来减小施加在通孔上的拉伸应力。
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