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公开(公告)号：US10218341B2
公开(公告)日：2019-02-26
申请号：US15812780
申请日：2017-11-14
Applicant: Marvell World Trade Ltd.
Inventor： Luns Tee , Wanghua Wu , Xiang Gao
Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.
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2.发明申请公开(公告)号：US20180138899A1
公开(公告)日：2018-05-17
申请号：US15812780
申请日：2017-11-14
Applicant: Marvell World Trade Ltd.
Inventor： Luns Tee , Wanghua Wu , Xiang Gao
CPC classification number: H03K5/135 , H03L7/0992 , H03L7/10 , H03L7/18 , H03L7/1974 , H03L7/1976 , H03L7/23 , H03L2207/06 , H03L2207/12
Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.
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公开(公告)号：US09966937B2
公开(公告)日：2018-05-08
申请号：US15184342
申请日：2016-06-16
Applicant: Marvell World Trade LTD.
Inventor： Mustafa Oguzhan Yayla , Xiang Gao , Li Lin
CPC classification number: H03K5/00006 , H03B19/14 , H03B2200/007 , H03B2202/05 , H03K3/0315
Abstract: A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.
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Patent Agency Ranking
公开(公告)号：US20160373094A1
公开(公告)日：2016-12-22
申请号：US15184342
申请日：2016-06-16
Applicant: Marvell World Trade LTD.
Inventor： Mustafa Oguzhan YAYLA , Xiang Gao , Li Lin
CPC classification number: H03K5/00006 , H03B19/14 , H03B2200/007 , H03B2202/05 , H03K3/0315
Abstract: A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.
Abstract translation: 系统包括信号发生器和信号组合器。 信号发生器被配置为输出具有第一频率的第一信号，并输出具有第一频率的一个或多个信号，并且具有相对于第一信号相移一定预定量的相位。 信号组合器被配置为组合第一信号和一个或多个信号以输出具有第二频率的倍频的第二信号。 第二个频率大于第一个频率。
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公开(公告)号：US20170366376A1
公开(公告)日：2017-12-21
申请号：US15629509
申请日：2017-06-21
Applicant: Marvell World Trade Ltd.
Inventor： Haisong Wang , Xiang Gao , Olivier Burg , Cao-Thong Tu
CPC classification number: H04L27/2017 , H03L7/081 , H03L7/087 , H03L7/093 , H03L7/1976 , H03L2207/06 , H04L25/03834 , H04L27/0014
Abstract: An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.
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公开(公告)号：US09740175B2
公开(公告)日：2017-08-22
申请号：US15370796
申请日：2016-12-06
Applicant: Marvell World Trade Ltd.
Inventor： Olivier Burg , Haisong Wang , Xiang Gao
CPC classification number: G04F10/005 , H03B21/02 , H03L7/0891 , H03L7/091 , H03L7/0991 , H03L7/18 , H03M1/00 , H03M1/12 , H03M1/50 , H03M7/3004 , H03M2201/4233 , H04M1/505
Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.
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公开(公告)号：US09356612B2
公开(公告)日：2016-05-31
申请号：US14540485
申请日：2014-11-13
Applicant: MARVELL WORLD TRADE LTD
CPC classification number: H03L7/18 , H03L7/085 , H03L7/091 , H03L7/099 , H03L7/0992 , H03L7/183 , H03L7/197
Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.
Abstract translation: 本公开的方面提供了一种包括检测器，环路滤波器和控制器的电路。 检测器被配置为产生指示参考时钟信号和反馈时钟信号之间的定时差的第一信号。 基于来自振荡器的振荡信号产生反馈时钟信号。 振荡器包括第一调谐电路和调谐振荡信号的频率的第二调谐电路。 环路滤波器被配置为从第一信号滤出一部分频率分量以产生用于调谐振荡器的第一调谐电路的第二信号。 控制器被配置为基于第一信号和第二信号来调谐第二调谐电路。
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8.发明申请公开(公告)号：US20190393867A1
公开(公告)日：2019-12-26
申请号：US16284773
申请日：2019-02-25
Applicant: Marvell World Trade Ltd.
Inventor： Luns Tee , Wanghua Wu , Xiang Gao
Abstract: Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal.
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