公开(公告)号：US20100264551A1

公开(公告)日：2010-10-21

申请号：US12426466

申请日：2009-04-20

申请人： MUKTA G. FAROOQ ,  ROBERT HANNON ,  SUBRAMANIAN S. IYER ,  EMILY R. KINSER

发明人： MUKTA G. FAROOQ ,  ROBERT HANNON ,  SUBRAMANIAN S. IYER ,  EMILY R. KINSER

IPC分类号： H01L25/065 ,  H01L21/50

CPC分类号： H01L21/76898 ,  H01L24/06 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00

摘要： A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

摘要翻译： 实现多集成电路（IC）器件的三维（3D）集成的方法包括在第一IC器件上形成第一绝缘层; 在第二IC器件上形成第二绝缘层; 通过将第一绝缘层对准和结合到第二绝缘层来形成3D粘合IC器件，以便在它们之间限定其间的接合界面，限定3D结合IC器件内的第一组通孔，第一组通孔在导电 位于所述第一IC器件内的焊盘，以及限定所述3D结合IC器件内的第二组通孔，所述第二组通孔着陆在位于所述第二器件内的导电焊盘上，使得所述第二组通孔穿过所述接合界面; 以及用导电材料填充第一组和第二组通孔。

公开(公告)号：US20130119509A1

公开(公告)日：2013-05-16

申请号：US13297338

申请日：2011-11-16

申请人： MUKTA G. FAROOQ ,  Emily R. Kinser

发明人： MUKTA G. FAROOQ ,  Emily R. Kinser

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.

公开(公告)号：US20110079907A1

公开(公告)日：2011-04-07

申请号：US12573183

申请日：2009-10-05

申请人： MUKTA G. FAROOQ ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

发明人： MUKTA G. FAROOQ ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.

摘要翻译： 公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。 还公开了制造半导体器件的方法。

公开(公告)号：US20090155983A1

公开(公告)日：2009-06-18

申请号：US11955484

申请日：2007-12-13

申请人： MUKTA G. FAROOQ ,  ROBERT HANNON ,  DAE-YOUNG JUNG

发明人： MUKTA G. FAROOQ ,  ROBERT HANNON ,  DAE-YOUNG JUNG

IPC分类号： H01L21/304

CPC分类号： H01L21/02076

摘要： Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.

摘要翻译： 提供了抑制激光切割引起的金属扩散的方法。 该方法包括将晶片分成至少一个芯片。 该芯片包括内部金属特征。 分散在芯片的外表面上沉积至少一种金属物质。 在分割芯片之后，该方法将芯片暴露于具有给定压力（例如，小于一个大气压）的加热的环境环境中。 环境包括能够与金属物质结合的化学试剂。 另外，可以在芯片上进行湿式化学蚀刻。

公开(公告)号：US20110193197A1

公开(公告)日：2011-08-11

申请号：US12700841

申请日：2010-02-05

申请人： MUKTA G. FAROOQ ,  JOHN A. GRIESEMER ,  WILLIAM F. LANDERS ,  IAN D. MELVILLE ,  THOMAS M. SHAW ,  HUILONG ZHU

发明人： MUKTA G. FAROOQ ,  JOHN A. GRIESEMER ,  WILLIAM F. LANDERS ,  IAN D. MELVILLE ,  THOMAS M. SHAW ,  HUILONG ZHU

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L21/98

CPC分类号： H01L23/5226 ,  H01L21/2007 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.

摘要翻译： 公开了一种用于防止裂纹传播到3D集成电路的有源区域的结构，例如由薄化的衬底层或接合层的外围处的缺陷引发的裂纹及其形成方法。