公开(公告)号：US20080143421A1

公开(公告)日：2008-06-19

申请号：US11979405

申请日：2007-11-02

申请人： Manabu Yanagihara ,  Tatsuo Morita ,  Yasuhiro Uemoto

发明人： Manabu Yanagihara ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC分类号： H03K17/687

CPC分类号： H03K17/6874 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786 ,  H03K17/063 ,  H03K17/567 ,  H03K17/725

摘要： A bidirectional switch comprises a first FET, a second FET, and a switch controller for controlling a conductive state in which current from a bidirectional power supply electrically connected to drain terminals bidirectionally flows, and a nonconductive state in which the current does not flow. In the conductive state, the switch controller applies, to gate terminals of the first FET and the second FET, a voltage higher than a threshold voltage with reference to a potential at a node to which source terminals of the first FET and the second FET are connected. In the nonconductive state, the switch controller causes the bidirectional power supply and each gate terminal to be electrically insulated from each other, and applies a voltage lower than or equal to the threshold voltage with reference to the potential at the node.

摘要翻译： 双向开关包括第一FET，第二FET和开关控制器，用于控制来自双向电源电连接到漏极端子的电流双向流动的导通状态以及电流不流动的非导通状态。 在导通状态下，开关控制器参照第一FET和第二FET的源极端子处的电位，向第一FET和第二FET的栅极端子施加高于阈值电压的电压 连接的。 在非导通状态下，开关控制器使得双向电源和每个栅极端子彼此电绝缘，并且参考节点处的电位施加低于或等于阈值电压的电压。

公开(公告)号：US08344463B2

公开(公告)日：2013-01-01

申请号：US12681567

申请日：2009-07-10

申请人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

发明人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC分类号： H01L27/88

CPC分类号： H01L27/088 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

摘要翻译： 双向开关包括多个单元电池11，其包括第一欧姆电极15，第一栅极电极17，第二栅极电极18和第二欧姆电极16.第一栅电极15经由第一互连线31电连接到 第一栅极电极焊盘43.第二栅电极18经由第二互连32电连接到第二栅极电极焊盘44.单元电池11包括与第一栅电极焊盘43的布线距离最短的第一栅电极17 包括与第二栅电极焊盘44的互连距离最短的第二栅电极18。

公开(公告)号：US08405126B2

公开(公告)日：2013-03-26

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03K17/687

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US20110284928A1

公开(公告)日：2011-11-24

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778 ,  H01L27/06

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US20100213503A1

公开(公告)日：2010-08-26

申请号：US12681567

申请日：2009-07-10

申请人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

发明人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC分类号： H01L29/747

CPC分类号： H01L27/088 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

摘要翻译： 双向开关包括多个单元电池11，其包括第一欧姆电极15，第一栅极电极17，第二栅极电极18和第二欧姆电极16.第一栅电极15经由第一互连线31电连接到 第一栅极电极焊盘43.第二栅电极18经由第二互连32电连接到第二栅极电极焊盘44.单元电池11包括与第一栅电极焊盘43的布线距离最短的第一栅电极17 包括与第二栅电极焊盘44的互连距离最短的第二栅电极18。

公开(公告)号：US20090166677A1

公开(公告)日：2009-07-02

申请号：US12329939

申请日：2008-12-08

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L21/338 ,  H01L29/812

CPC分类号： H01L29/7783 ,  H01L21/26533 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7781 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device includes: a semiconductor substrate; a diode having a cathode formed on a first surface side of the semiconductor substrate and an anode formed on a second surface side of the semiconductor substrate; and a transistor formed over the semiconductor substrate. The transistor includes a semiconductor layer laminate formed over the semiconductor substrate, a source electrode and a drain electrode that are formed spaced apart from each other over the semiconductor layer laminate, and a gate electrode formed between the source electrode and the drain electrode. The source electrode is electrically connected to the anode, and the drain electrode is electrically connected to the cathode.

摘要翻译： 半导体器件包括：半导体衬底; 具有形成在半导体衬底的第一表面侧的阴极和形成在半导体衬底的第二表面侧上的阳极的二极管; 以及形成在半导体衬底上的晶体管。 晶体管包括形成在半导体衬底上的半导体层叠层，在半导体层叠层上彼此隔开形成的源电极和漏极，以及形成在源电极和漏电极之间的栅电极。 源电极与阳极电连接，漏电极与阴极电连接。

公开(公告)号：US08497581B2

公开(公告)日：2013-07-30

申请号：US13220054

申请日：2011-08-29

申请人： Ayanori Ikoshi ,  Yasuhiro Uemoto ,  Manabu Yanagihara ,  Tatsuo Morita

发明人： Ayanori Ikoshi ,  Yasuhiro Uemoto ,  Manabu Yanagihara ,  Tatsuo Morita

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/34

CPC分类号： H01L24/11 ,  H01L23/295 ,  H01L23/3192 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4824 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29076 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.

摘要翻译： 半导体器件包括：半导体芯片; 依次堆叠在半导体芯片上的保护膜和绝缘膜，并且每个具有暴露源极，漏极和栅极焊盘的开口; 由具有比绝缘膜高的导热性的材料制成的散热端子; 形成在源极，漏极和栅极焊盘上并被绝缘膜包围的连接端子; 以及具有连接焊盘的安装基板。 半导体芯片具有具有多个源极指的源极，具有多个漏极指的漏电极和具有多个栅极指的栅电极。 源极，漏极和栅极焊盘分别连接到源电极，漏极电极和栅电极。 连接端子分别连接到连接焊盘。 散热端与安装基板紧密接触。

公开(公告)号：US20120001200A1

公开(公告)日：2012-01-05

申请号：US13220054

申请日：2011-08-29

申请人： Ayanori Ikoshi ,  Yasuhiro Uemoto ,  Manabu Yanagihara ,  Tatsuo Morita

发明人： Ayanori Ikoshi ,  Yasuhiro Uemoto ,  Manabu Yanagihara ,  Tatsuo Morita

IPC分类号： H01L29/161 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L23/295 ,  H01L23/3192 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4824 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29076 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.

摘要翻译： 半导体器件包括：半导体芯片; 依次堆叠在半导体芯片上的保护膜和绝缘膜，并且每个具有暴露源极，漏极和栅极焊盘的开口; 由具有比绝缘膜高的导热性的材料制成的散热端子; 形成在源极，漏极和栅极焊盘上并被绝缘膜包围的连接端子; 以及具有连接焊盘的安装基板。 半导体芯片具有具有多个源极指的源极，具有多个漏极指的漏电极和具有多个栅极指的栅电极。 源极，漏极和栅极焊盘分别连接到源电极，漏极电极和栅电极。 连接端子分别连接到连接焊盘。 散热端与安装基板紧密接触。

公开(公告)号：US20100321363A1

公开(公告)日：2010-12-23

申请号：US12518005

申请日：2008-06-19

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Manabu Inoue

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Manabu Inoue

IPC分类号： G09G3/28

CPC分类号： G09G3/294 ,  G09G3/2965

摘要： A plasma display panel driving device includes an electrode driving unit for generating a drive pulse to be applied to an electrode of a plasma display panel. The electrode driving unit has a plurality of switches. At least one of the plurality of switches is a switch device including a dual-gate semiconductor device. The dual-gate semiconductor device 10 has a semiconductor multilayer 13 formed on a substrate 11 and made of a nitride semiconductor or a silicon carbide semiconductor, a source electrode 16 and a drain electrode 17 formed and spaced apart from each other on the semiconductor multilayer 13, and a first gate electrode 18A and a second gate electrode 18B formed between the source electrode 16 and the drain electrode 17, successively from the source electrode 16 side.

摘要翻译： 等离子体显示面板驱动装置包括用于产生施加到等离子体显示面板的电极的驱动脉冲的电极驱动单元。 电极驱动单元具有多个开关。 多个开关中的至少一个是包括双栅极半导体器件的开关器件。 双栅极半导体器件10具有形成在基板11上并由氮化物半导体或碳化硅半导体形成的半导体层叠体13，在半导体层叠体13上形成并隔开的源电极16和漏电极17 以及从源极电极16侧依次形成在源极电极16和漏极电极17之间的第一栅极电极18A和第二栅极电极18B。