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    Method And Structure For Compound Semiconductor Contact
    2.
    发明申请
    Method And Structure For Compound Semiconductor Contact 有权
    化合物半导体接触的方法与结构

    公开(公告)号：US20120261718A1

    公开(公告)日：2012-10-18

    申请号：US13085511

    申请日：2011-04-13

    申请人： Norma E. Sosa Cortes ,  Edward W. Kiewra ,  Masaharu Kobayashi ,  Kuen-Ting Shiu

    发明人： Norma E. Sosa Cortes ,  Edward W. Kiewra ,  Masaharu Kobayashi ,  Kuen-Ting Shiu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66522 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7838 ,  H01L29/7848

    摘要： The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.

    摘要翻译： 本公开提供了掩埋沟道半导体结构，其中使用结晶湿蚀刻来定制形成多层衬底的蚀刻区域的轮廓，其包括位于掩埋半导体沟道材料层顶部的化合物半导体层。 在化合物半导体上使用结晶湿式蚀刻可以使形成多层基板的源极凹部区域和漏极凹陷区域的形状成为可能。 这允许控制栅极重叠/欠压。 此外，在化合物半导体上使用晶体湿式蚀刻可以独立控制下面的掩埋半导体沟道区的长度。

    Gate-array type intergated circuit semiconductor device
    7.
    发明授权
    Gate-array type intergated circuit semiconductor device 失效
    门阵列型中间电路半导体器件

    公开(公告)号：US4984050A

    公开(公告)日：1991-01-08

    申请号：US297628

    申请日：1989-01-13

    申请人： Masaharu Kobayashi

    发明人： Masaharu Kobayashi

    IPC分类号： H01L21/768 ,  H01L21/82 ,  H01L23/522 ,  H01L27/118

    CPC分类号： H01L27/11801 ,  H01L2924/0002 ,  Y10S257/903 ,  Y10S257/906

    摘要： A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cells. A field insulating layer is also formed on the substrate, which is partially embedded in the major surface of the substrate and is formed entirely on a wiring channel forming portion of the substrate and selectively on the basic cell forming portion of the same to surround each of the impurity regions. An insulating film is formed on the field insulating layer. A wiring structure is provided, which includes mutual wirings formed of a first level conductive layer, internal wirings, and interconnecting wirings formed of a second level conductive layer higher than the first level conductive layer. Each of the mutual wirings is formed only on the insulating film formed on the wiring channel forming portion and is connected to the impurity regions through the interconnecting and internal wirings.

    摘要翻译： 门阵列型集成电路半导体器件包括半导体衬底，其基本单元形成部分形成有多个基本电路元件的杂质区域。 杂质区形成多个碱性电池。 场致绝缘层也形成在衬底上，该衬底被部分地嵌入衬底的主表面中，并且整体地形成在衬底的布线沟道形成部分上，并且选择性地在其基本单元形成部分上围绕 杂质区。 在场绝缘层上形成绝缘膜。 提供一种布线结构，其包括由第一层导电层，内部布线和由比第一层导电层高的第二层导电层形成的互连布线形成的互连。 每个相互配线仅形成在形成在布线沟道形成部分上的绝缘膜上，并且通过互连和内部布线连接到杂质区域。

    Digital signal transmission method providing high error correction capability
    9.
    发明授权
    Digital signal transmission method providing high error correction capability 失效
    数字信号传输方式提供高纠错能力

    公开(公告)号：US4649542A

    公开(公告)日：1987-03-10

    申请号：US621743

    申请日：1984-06-18

    申请人： Keizo Nishimura ,  Masaharu Kobayashi ,  Hiroo Okamoto ,  Takaharu Noguchi ,  Takao Arai ,  Toshifumi Shibuya

    发明人： Keizo Nishimura ,  Masaharu Kobayashi ,  Hiroo Okamoto ,  Takaharu Noguchi ,  Takao Arai ,  Toshifumi Shibuya

    IPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/27 ,  G06F11/10

    CPC分类号： G11B20/1809

    摘要： A method of transmitting a digital signal in the form of successive signal frames containing codes for detecting and correcting errors of the digital signal for reducing degradation in the quality of the reproduced sound due to generation of the code errors in a digitized audio signal transmission system. An analog signal such as an audio signal is sampled and subjected to A/D conversion. The sample word thus obtained is divided into a plurality of symbol elements. Parity words for detecting and correcting code errors are added to every group of a predetermined number of the information symbols through an interleave procedure before being transmitted. The method includes the steps of applying a first frame of symbols, taken one from each input channel, and having a first arrangement state, to a first error-correcting code encoder to generate a series of first parity words; delaying each of the symbols in the first frame and each of the first parity words by a respective different delay time in a unit of the sample word at a delay line to provide a resulting second frame of symbols in a second arrangement state; applying the second frame of symbols to a second error-correcting code encoder to generate a series of second parity words; and transmitting said second frame of symbols together with said second parity words.

    摘要翻译： 以包含用于检测和校正数字信号的错误的代码的连续信号帧的形式发送数字信号的方法，用于减少由于数字化音频信号传输系统中的代码错误的产生而导致的再现声音质量的劣化。 诸如音频信号的模拟信号被采样并进行A / D转换。 由此获得的采样字被分成多个符号元素。 用于检测和校正码错误的奇偶校验字在发送之前通过交织过程被添加到预定数量的信息符号的每个组中。 该方法包括以下步骤：将第一帧符号从每个输入通道中取出并具有第一布置状态到第一纠错码编码器以产生一系列第一奇偶校验字; 延迟第一帧和第一奇偶校验字中的每个符号以延迟线为单位的采样字的相应的不同延迟时间，以在第二布置状态下提供所得到的第二符号帧; 将第二符号帧应用于第二纠错码编码器以产生一系列第二奇偶校验字; 以及与所述第二奇偶校验字一起发送所述第二符号帧。