利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.022 秒)

    LIGHT EMITTING DEVICE FOR AC POWER OPERATION
    3.
    发明申请
    LIGHT EMITTING DEVICE FOR AC POWER OPERATION 有权
    用于交流电源运行的发光装置

    公开(公告)号：US20110031891A1

    公开(公告)日：2011-02-10

    申请号：US12908692

    申请日：2010-10-20

    申请人： Chung Hoon LEE ,  James S. SPECK ,  Hong San KIM ,  Jae Jo KIM ,  Sung Han KIM ,  Jae Ho LEE

    发明人： Chung Hoon LEE ,  James S. SPECK ,  Hong San KIM ,  Jae Jo KIM ,  Sung Han KIM ,  Jae Ho LEE

    IPC分类号： H05B41/16

    CPC分类号： H05B33/0827 ,  H01L27/153 ,  H01L27/156 ,  H01L2224/48137 ,  H01L2224/49107 ,  H01L2224/73265 ,  H05B33/02 ,  H05B33/08 ,  H05B33/0806 ,  H05B33/0815 ,  H05B33/0821 ,  H05B33/0824 ,  H05B33/083 ,  H05B33/0848 ,  H05B37/029

    摘要： Disclosed is an improved light-emitting device for an AC power operation. A conventional light emitting device employs an AC light-emitting diode having arrays of light emitting cells connected in reverse parallel. The arrays in the prior art alternately repeat on/off in response to a phase change of an AC power source, resulting in short light emission time during a ½ cycle and the occurrence of a flicker effect. An AC light-emitting device according to the present invention employs a variety of means by which light emission time is prolonged during a ½ cycle in response to a phase change of an AC power source and a flicker effect can be reduced. For example, the means may be switching blocks respectively connected to nodes between the light emitting cells, switching blocks connected to a plurality of arrays, or a delay phosphor. Further, there is provided an AC light-emitting device, wherein a plurality of arrays having the different numbers of light emitting cells are employed to increase light emission time and to reduce a flicker effect.

    摘要翻译： 公开了一种用于AC电力操作的改进的发光装置。 传统的发光器件采用具有反向并联连接的发光单元阵列的交流发光二极管。 现有技术中的阵列响应于AC电源的相变而交替重复开/关，导致在1/2周期期间的短发光时间和闪烁效应的发生。 根据本发明的交流发光装置采用各种手段，响应于​​交流电源的相变而在1/2周期期间发光时间延长，并且可以减少闪烁效应。 例如，装置可以是分别连接到发光单元，连接到多个阵列的切换块或延迟荧光体之间的节点的切换块。 此外，提供了一种交流发光装置，其中采用具有不同数量的发光单元的多个阵列来增加发光时间并减少闪烁效果。

    METHOD OF FORMING P-TYPE COMPOUND SEMICONDUCTOR LAYER
    4.
    发明申请
    METHOD OF FORMING P-TYPE COMPOUND SEMICONDUCTOR LAYER 有权
    形成P型复合半导体层的方法

    公开(公告)号：US20100003810A1

    公开(公告)日：2010-01-07

    申请号：US12560891

    申请日：2009-09-16

    申请人： Ki Bum NAM ,  Hwa Mok KIM ,  James S. SPECK

    发明人： Ki Bum NAM ,  Hwa Mok KIM ,  James S. SPECK

    IPC分类号： H01L21/20

    CPC分类号： H01L33/007 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262

    摘要： A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.

    摘要翻译： 形成p型化合物半导体层的方法包括将装载到反应室中的基板的温度升高到第一温度。 将III族元素的源气体，p型杂质的源气体和含氮气的源气体供给到反应室中以使p型化合物半导体层生长。 然后，停止供给III族元素的源气体和p型杂质的源气体，并将基板的温度降低到第二温度。 供给含氮氢气的源气体在第二温度下停止并排出，并且使用冷却气体将基板的温度降至室温。 因此，防止氢与p型化合物半导体层中的p型杂质结合。

    SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N
    6.
    发明申请
    SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N 有权
    通过在非C平面上的硅掺杂（Al，Ga，In）N来抑制密封形成和增加关键厚度的抑制

    公开(公告)号：US20120286241A1

    公开(公告)日：2012-11-15

    申请号：US13470598

    申请日：2012-05-14

    申请人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. SPECK ,  Shuji Nakamura

    发明人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. SPECK ,  Shuji Nakamura

    IPC分类号： H01L49/00 ,  H01L21/20

    CPC分类号： H01L21/0254 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02513

    摘要： A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.

    摘要翻译： 一种用于制造III族氮化物的半导体器件的方法，包括（a）在半极性或非极性GaN衬底上或之上生长一个或多个缓冲层，其中缓冲层是半极性或非极性III- 氮化物缓冲层; 并且（b）掺杂缓冲层，使得形成在掺杂缓冲层上或上方的III族氮化物器件层中的多个晶体缺陷不高于形成在一个或多个第一或第二晶体管上形成的III族氮化物器件层中的多个晶体缺陷 更多未掺杂的缓冲层。 掺杂可以减少或防止错配位错线的形成和额外的穿线位错。 缓冲层的厚度和/或组成可以使得缓冲层的厚度接近或大于其缓解的临界厚度。 此外，可以在缓冲层上或上方形成一个或多个（AlInGaN）或III族氮化物器件层。