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    Suppression of inclined defect formation and increase in critical thickness by silicon doping on non-c-plane (Al,Ga,In)N
    4.
    发明授权
    Suppression of inclined defect formation and increase in critical thickness by silicon doping on non-c-plane (Al,Ga,In)N 有权
    通过硅掺杂在非c面（Al，Ga，In）N上抑制倾斜缺陷形成和临界厚度增加

    公开(公告)号：US08772758B2

    公开(公告)日：2014-07-08

    申请号：US13470598

    申请日：2012-05-14

    申请人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

    发明人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

    IPC分类号： H01L29/06

    CPC分类号： H01L21/0254 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02513

    摘要： A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.

    摘要翻译： 一种用于制造III族氮化物的半导体器件的方法，包括（a）在半极性或非极性GaN衬底上或之上生长一个或多个缓冲层，其中缓冲层是半极性或非极性III- 氮化物缓冲层; 并且（b）掺杂缓冲层，使得形成在掺杂缓冲层上或上方的III族氮化物器件层中的多个晶体缺陷不高于形成在一个或多个第一或第二晶体管上形成的III族氮化物器件层中的多个晶体缺陷 更多未掺杂的缓冲层。 掺杂可以减少或防止错配位错线的形成和额外的穿线位错。 缓冲层的厚度和/或组成可以使得缓冲层的厚度接近或大于其缓解的临界厚度。 此外，可以在缓冲层上或上方形成一个或多个（AlInGaN）或III族氮化物器件层。

    SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N
    6.
    发明申请
    SUPPRESSION OF INCLINED DEFECT FORMATION AND INCREASE IN CRITICAL THICKNESS BY SILICON DOPING ON NON-C-PLANE (Al,Ga,In)N 有权
    通过在非C平面上的硅掺杂（Al，Ga，In）N来抑制密封形成和增加关键厚度的抑制

    公开(公告)号：US20120286241A1

    公开(公告)日：2012-11-15

    申请号：US13470598

    申请日：2012-05-14

    申请人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. SPECK ,  Shuji Nakamura

    发明人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. SPECK ,  Shuji Nakamura

    IPC分类号： H01L49/00 ,  H01L21/20

    CPC分类号： H01L21/0254 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02513

    摘要： A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.

    摘要翻译： 一种用于制造III族氮化物的半导体器件的方法，包括（a）在半极性或非极性GaN衬底上或之上生长一个或多个缓冲层，其中缓冲层是半极性或非极性III- 氮化物缓冲层; 并且（b）掺杂缓冲层，使得形成在掺杂缓冲层上或上方的III族氮化物器件层中的多个晶体缺陷不高于形成在一个或多个第一或第二晶体管上形成的III族氮化物器件层中的多个晶体缺陷 更多未掺杂的缓冲层。 掺杂可以减少或防止错配位错线的形成和额外的穿线位错。 缓冲层的厚度和/或组成可以使得缓冲层的厚度接近或大于其缓解的临界厚度。 此外，可以在缓冲层上或上方形成一个或多个（AlInGaN）或III族氮化物器件层。