公开(公告)号：US08436404B2

公开(公告)日：2013-05-07

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09093513B2

公开(公告)日：2015-07-28

申请号：US13786372

申请日：2013-03-05

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L21/336 ,  H01L21/28 ,  H01L21/463 ,  H01L29/78 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20130178033A1

公开(公告)日：2013-07-11

申请号：US13786372

申请日：2013-03-05

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20170040218A1

公开(公告)日：2017-02-09

申请号：US15299106

申请日：2016-10-20

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/51

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20110156107A1

公开(公告)日：2011-06-30

申请号：US12655408

申请日：2009-12-30

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US09054178B2

公开(公告)日：2015-06-09

申请号：US14174822

申请日：2014-02-06

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20140151817A1

公开(公告)日：2014-06-05

申请号：US14174822

申请日：2014-02-06

申请人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

发明人： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhai-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC分类号： H01L29/78 ,  H01L29/51

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

摘要翻译： 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US20150069473A1

公开(公告)日：2015-03-12

申请号：US14020299

申请日：2013-09-06

申请人： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Michael L. Hattendorf ,  Subhash M. Joshi

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Michael J. Jackson ,  Michael L. Hattendorf ,  Subhash M. Joshi

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L21/768

CPC分类号： H01L21/02175 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

摘要翻译： 公开了用于晶体管制造的技术，包括用于源极/漏极（S / D）区域的牺牲保护层以使接触电阻最小化。 牺牲保护层可以在形成这些区域之后但在S / D区域上沉积绝缘体层之前选择性地沉积在S / D区域上。 随后，在进行接触沟槽蚀刻之后，可执行额外的蚀刻工艺以去除牺牲保护层并暴露干净的S / D表面。 因此，牺牲保护层可以保护S / D区域的接触位置免受由绝缘体层沉积引起的污染（例如，氧化或氮化）。 牺牲保护层还可以将S / D区域保护在残留在S / D接触表面上的不期望的绝缘体材料，特别是对于非平面晶体管结构（例如，鳍状或纳米线/纳米级晶体管结构）。

公开(公告)号：US06853076B2

公开(公告)日：2005-02-08

申请号：US09961034

申请日：2001-09-21

申请人： Madhav Datta ,  Dave Emory ,  Subhash M. Joshi ,  Susanne Menezes ,  Doowon Suh

发明人： Madhav Datta ,  Dave Emory ,  Subhash M. Joshi ,  Susanne Menezes ,  Doowon Suh

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

摘要翻译： 本发明涉及一种用于电气装置的极限极限冶金堆，其包含设置在Ti粘附金属层上的至少一个铜层。 限流冶金叠层可阻止Sn向器件的上部金属化迁移。

公开(公告)号：US08377771B2

公开(公告)日：2013-02-19

申请号：US13479078

申请日：2012-05-23

申请人： Willy Rachmady ,  Brian McIntrye ,  Michael K. Harper ,  Subhash M. Joshi

发明人： Willy Rachmady ,  Brian McIntrye ,  Michael K. Harper ,  Subhash M. Joshi

IPC分类号： H01L21/8238

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/66553

摘要： A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.

摘要翻译： 晶体管栅极包括具有设置在表面上的一对间隔物的衬底，在隔离体之间保形地沉积在衬底上的高k电介质，共形沉积在高k电介质上并沿着间隔壁侧壁的一部分的凹陷功函数金属 保形地沉积在凹陷功函数金属上的第二功函件金属和沉积在第二功函数金属上的电极金属。 晶体管栅极可以通过将高k电介质保形地沉积到衬底上的间隔物之间​​的沟槽中而形成，从而在高k电介质顶部上共形沉积功函数金属，在功函数金属顶部沉积牺牲掩模，蚀刻部分 牺牲掩模以暴露所述功函数金属的一部分，以及蚀刻所述功函数金属的暴露部分以形成所述凹陷功函数金属。 第二功函数金属和电极金属可沉积在凹陷功函数金属顶上。