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    Semiconductor integrated circuit having multiple self-test functions and operating method therefor
    3.
    发明授权
    Semiconductor integrated circuit having multiple self-test functions and operating method therefor 失效
    具有多个自检功能的半导体集成电路及其操作方法

    公开(公告)号：US4970727A

    公开(公告)日：1990-11-13

    申请号：US263118

    申请日：1988-10-27

    申请人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

    发明人： Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Takeshi Nakayama ,  Kazuo Kobayashi ,  Yasushi Terada

    IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G11C16/02 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

    CPC分类号： G11C29/46 ,  G01R31/31701

    摘要： In a semiconductor integrated circuit such as a semiconductor memory device capable of operating in a special mode in addition to a standard operation mode, a high voltage detection circuit 10 detects a high voltage applied to one of control signal input terminals CS and outputs a detection signal HV to a special mode circuit 14. The special mode circuit 14 outputs a switch signal CO to a switching circuit 11 in response to the detection signal HV. The switching circuit 11 connects an input/output buffer 7 to a latch circuit 12 in response to the switch signal CO. A special mode code MC is applied to input/output terminals DT and transmitted to the latch circuit 12 through the switching circuit 11. A special mode decoder 13 decodes the special mode code MC which has been latched by the latch circuit 12 and outputs a signal for specifying the special mode to a control circuit 8. Operation in the special mode specified by the control circuit 8 is executed. By detecting a confirmation signal CS applied to one of the control signal input terminals CS during the execution of the special mode, the special mode code MC which has been already latched by the latch circuit 12 can be outputted from the input/output terminals DT.

    摘要翻译： 在除了标准工作模式之外能够以特殊模式工作的半导体存储器件的半导体集成电路中，高电压检测电路10检测施加到控制信号输入端子CS之一的高电压，并输出检测信号 HV到特殊模式电路14.特殊模式电路14响应于检测信号HV将开关信号CO输出到开关电路11。 开关电路11响应于开关信号CO将输入/输出缓冲器7连接到锁存电路12.特殊模式代码MC被施加到输入/输出端子DT，并通过开关电路11发送到锁存电路12。 特殊模式解码器13解码由锁存电路12锁存的特殊模式代码MC，并将用于指定特殊模式的信号输出到控制电路8.执行由控制电路8指定的特殊模式中的操作。 通过检测在特殊模式执行期间施加到控制信号输入端子CS之一的确认信号CS，可以从输入/输出端子DT输出已被锁存电路12锁存的特殊模式代码MC。

    Non-volatile semiconductor memory device
    4.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5283758A

    公开(公告)日：1994-02-01

    申请号：US794708

    申请日：1991-11-20

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Kazuo Kobayashi ,  Masanori Hayashikoshi ,  Yoshikazu Miyawaki

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C16/16 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0425 ,  G11C16/0491 ,  G11C7/18

    摘要： A plurality of memory cell transistors having floating gates are disposed in a matrix in the direction of row and column to form a memory cell array. The memory cell array is divided into a plurality of sectors for every predetermined row. In each sector, sector selecting transistors and sub bit lines are provided, so that erasing and programming can be made for each sector. Therefore, total erasing for sector becomes possible, and since no voltage is applied to sub bit lines and word lines of non-selected sectors, the number of operations of preventing writing into non-selected memory cells is as many as the word lines included in one sector.

    摘要翻译： 具有浮动栅极的多个存储单元晶体管以行和列的方向设置在矩阵中以形成存储单元阵列。 存储单元阵列被划分成用于每个预定行的多个扇区。 在每个扇区中，提供扇区选择晶体管和子位线，从而可以对每个扇区进行擦除和编程。 因此，扇区的全部擦除成为可能，并且由于没有电压施加到非选择扇区的子位线和字线，所以防止写入未选择的存储单元的操作次数与包括在 一个部门。

    Divided word line type non-volatile semiconductor memory device
    5.
    发明授权
    Divided word line type non-volatile semiconductor memory device 失效
    分字线型非易失性半导体存储器件

    公开(公告)号：US5132928A

    公开(公告)日：1992-07-21

    申请号：US501703

    申请日：1990-03-30

    申请人： Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

    发明人： Masanori Hayashikoshi ,  Yasushi Terada ,  Kazuo Kobayashi ,  Takeshi Nakayama ,  Yoshikazu Miyawaki

    IPC分类号： G11C17/00 ,  G06F11/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C16/08 ,  G11C16/26

    摘要： An electrically programmable non-volatile semiconductor memory device includes a plurality of internal data transmission lines. Data communication between memory cells and the internal data transmission lines is performed for a byte of data having a plurality of bits. Each of the word lines includes a plurality of divided auxiliary word lines in association with the internal data transmission lines. Those memory cells for each word line that are to be connected to the same internal data transmission line are connected to one auxiliary word line. Only one of a plurality of memory cells connected to one auxiliary word line is connected to an internal data transmission line in operation. Therefore, a plurality of the memory cells connected to different auxiliary word lines, are connected in parallel to a plurality of the internal data transmission lines. According to this arrangement, the effect of word line destruction occasionally caused in one auxiliary word line is not extended to other auxiliary word lines, so that the damaged auxiliary word line can be repaired by the use of an error correction detection code.

    摘要翻译： 电可编程非易失性半导体存储器件包括多个内部数据传输线。 对于具有多个位的数据的字节执行存储器单元与内部数据传输线之间的数据通信。 每个字线包括与内部数据传输线相关联的多个划分的辅助字线。 要连接到同一内部数据传输线的每个字线的那些存储单元连接到一个辅助字线。 连接到一个辅助字线的多个存储单元中只有一个连接到操作中的内部数据传输线。 因此，连接到不同辅助字线的多个存储单元并联连接到多个内部数据传输线。 根据这种布置，偶然地在一个辅助字线中引起的字线破坏的影响不会扩展到其他辅助字线，从而可以通过使用纠错检测码修复损坏的辅助字线。

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5347490A

    公开(公告)日：1994-09-13

    申请号：US711532

    申请日：1991-06-10

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi

    IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/16 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  G11C11/34

    CPC分类号： G11C5/147 ,  G11C16/16 ,  G11C16/30

    摘要： Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

    摘要翻译： 公开了一种闪速EEPROM，其包括其中在存储单元中充分发生隧道现象的范围内将用作擦除脉冲源的外部施加的高电压降低到预定电压的电压降低电路。 由降压电路降低的电压被转换为宽度较小的脉冲，然后将转换的脉冲作为擦除脉冲施加到存储单元。 还公开了一种包括分为第一和第二块的存储单元阵列的闪存EEPROM。 提供了用于将由降压电路降低的电压作为擦除脉冲施加到存储单元的擦除脉冲施加电路，以及用于擦除验证的擦除验证电路用于第一和第二块中的每一个。 擦除脉冲施加电路和对应于第一块的擦除验证电路和对应于第二块的擦除验证电路被配置为独立地操作。

    Non-volatile semiconductor memory device
    7.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5554868A

    公开(公告)日：1996-09-10

    申请号：US300877

    申请日：1994-09-06

    申请人： Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    发明人： Masanori Hayashikoshi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  H01L29/788

    CPC分类号： G11C16/3404 ,  G11C16/3409

    摘要： There is a case where a memory cell brought to an over-erase (depletion) state if the erasing time is too long, for example, in an electrically erasable non-volatile semiconductor memory device. In this case, the transistor constituting the memory cell is always in ON state and causes erroneous operation. Therefore, it is detected whether there is any memory cell in the over-erase state or not after erasing in each memory cell, and if any memory cell is detected being in the over-erase state, tunnel writing is performed in each memory cell. Specifically, electrons are injected into the floating gate of the transistor constituting each memory cell by a tunnel phenomenon. This causes the memory cell in the over-erase state to recover to a normal state. Detection of the over-erase state and recovery from it are performed by an over-erase correcting circuit 72.

    摘要翻译： 如果擦除时间过长，例如在电可擦除非易失性半导体存储器件中存在存储器单元进入过擦除（耗尽）状态的情况。 在这种情况下，构成存储单元的晶体管总是处于导通状态并导致错误的操作。 因此，在每个存储单元中擦除之后检测是否存在处于过擦除状态的任何存储单元，并且如果检测到任何存储单元处于过擦除状态，则在每个存储单元中进行隧道写入。 具体地，电子通过隧道现象注入构成每个存储单元的晶体管的浮置栅极。 这使得处于过擦除状态的存储单元恢复到正常状态。 通过过擦除校正电路72执行过擦除状态和从其恢复的检测。

    Nonvolatile semiconductor memory device and data erasing method thereof
    8.
    发明授权
    Nonvolatile semiconductor memory device and data erasing method thereof 失效
    非易失性半导体存储器件及其数据擦除方法

    公开(公告)号：US5297096A

    公开(公告)日：1994-03-22

    申请号：US711547

    申请日：1991-06-07

    申请人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    发明人： Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Yoshikazu Miyawaki ,  Masanori Hayashikoshi ,  Tomoshi Futatsuya

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C16/14 ,  G11C16/16

    摘要： A flash EEPROM including a memory cell array divided into first and second blocks. Erase pulse applying circuits for applying erase pulses to memory cells and erase verifying circuits for erase-verifying the memory cells are provided one for each of those two blocks. The erase pulse applying circuit and the erase verifying circuit provided corresponding to the first block operate separately from the erase pulse applying circuit and the erase verifying circuit provided corresponding to the second block. The erase pulse applying circuits are each controlled by their corresponding erase verifying circuits. That is, each erase verifying circuit enables its corresponding erase pulse applying circuit only when detecting a memory cell in which a data erase is incomplete in the corresponding block.

    摘要翻译： 一种快闪EEPROM，包括分为第一和第二块的存储单元阵列。 为这两个块中的每一个提供擦除用于向存储单元施加擦除脉冲的脉冲施加电路和用于擦除验证存储单元的擦除验证电路。 对应于第一块设置的擦除脉冲施加电路和擦除验证电路与擦除脉冲施加电路和对应于第二块设置的擦除验证电路分开工作。 擦除脉冲施加电路各自由其相应的擦除验证电路控制。 也就是说，每个擦除验证电路仅在检测到相应块中的数据擦除不完整的存储单元时才能使其相应的擦除脉冲施加电路。

    Nonvolatile semiconductor memory device capable of erasing by a word line unit
    10.
    发明授权
    Nonvolatile semiconductor memory device capable of erasing by a word line unit 失效
    能够通过字线单元擦除的非易失性半导体存储器件

    公开(公告)号：US5402382A

    公开(公告)日：1995-03-28

    申请号：US942887

    申请日：1992-09-10

    申请人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    发明人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

    摘要翻译： 非易失性半导体存储器件具有多个存储单元，它们以具有行和列的矩阵形式布置，并且各自具有用于保持信息电荷的栅极，多个位线，多个字线，多个 源极线和用于产生负高电压的高压发生器。 高电压发生器连接到每个字线，并且响应于用于选择字线的信号，具有施加预定时钟的电容器。 半导体存储器件还包括擦除器件，其在擦除操作中将由高电压发生器产生的负高电压施加到由选择信号选择的字线。 擦除装置将连接到相应存储单元的源的源极线接地。