公开(公告)号：US5950078A

公开(公告)日：1999-09-07

申请号：US934347

申请日：1997-09-19

申请人： Masashi Maekawa ,  Jer-shen Maa

发明人： Masashi Maekawa ,  Jer-shen Maa

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/00 ,  H01L21/76

CPC分类号： H01L29/66757 ,  H01L21/2022

摘要： A method for rapid thermally annealing a thin amorphous film on a transparent substrate with the use of a radiation absorption film is provided. Unlike a transmissive silicon thin film, or transparent substrate, the metal absorptive film has excellent radiation absorption characteristics. When a radiation absorption layer is added to the substrate it is possible to rapidly anneal an amorphous silicon film with convention IC process radiation lamps. The metal absorption film also acts to conduct the heat to the amorphous silicon. The control provided by the choice of metal material, metal thickness, the oxidation of the metal surface, and the heat and duration of the RTA process provide unique opportunities to control the crystallization process. Polysilicon made by the above-described method has the potential of high electron mobility and low production costs. A thin-film structure for use in a TFT, made through the above-described method, is also provided.

摘要翻译： 提供了使用辐射吸收膜在透明基板上快速热退火薄非晶膜的方法。 与透射硅薄膜或透明基板不同，金属吸收膜具有优异的辐射吸收特性。 当向衬底添加辐射吸收层时，可以用常规IC工艺辐射灯快速退火非晶硅膜。 金属吸收膜还用于将热量传导到非晶硅。 通过金属材料的选择，金属厚度，金属表面的氧化以及RTA工艺的热和持续时间提供的控制提供了控制结晶过程的独特机会。 通过上述方法制造的多晶硅具有高电子迁移率和低生产成本的潜力。 还提供了通过上述方法制造的用于TFT的薄膜结构。

公开(公告)号：US20120015147A1

公开(公告)日：2012-01-19

申请号：US12836300

申请日：2010-07-14

申请人： Jer-shen Maa ,  Gregory S. Herman ,  Apostolos T. Voutsas

发明人： Jer-shen Maa ,  Gregory S. Herman ,  Apostolos T. Voutsas

IPC分类号： B32B5/16 ,  F24J2/02 ,  B05D5/12 ,  H01L31/052

CPC分类号： H01L31/0236 ,  H01L31/1884 ,  Y02E10/50 ,  Y10T428/24413

摘要： A solution process is provided for forming a textured transparent conductive oxide (TCO) film. The process provides a substrate, and forms a first layer on the substrate of metal oxide nanoparticles such as ZnO, In2O3, or SnO2. The metal oxide nanoparticles have a faceted structure with an average size greater than 100 nanometers (nm). Voids between the metal oxide nanoparticles have a size about equal to the size of the metal oxide nanoparticles. Then, a second layer is formed overlaying the first layer, filling the voids between the nanoparticles of the first layer, and completely covering the substrate. The result is a continuous TCO film having an average surface roughness that is created by the combination of first and second layers.

摘要翻译： 提供了一种用于形成织构化的透明导电氧化物（TCO）膜的溶液方法。 该方法提供了一种衬底，并在诸如ZnO，In 2 O 3或SnO 2的金属氧化物纳米颗粒的衬底上形成第一层。 金属氧化物纳米颗粒具有平均尺寸大于100纳米（nm）的刻面结构。 金属氧化物纳米颗粒之间的空隙的尺寸大约等于金属氧化物纳米颗粒的尺寸。 然后，形成覆盖第一层的第二层，填充第一层的纳米颗粒之间的空隙，并完全覆盖基底。 结果是具有由第一层和第二层的组合产生的平均表面粗糙度的连续的TCO膜。

公开(公告)号：US07384837B2

公开(公告)日：2008-06-10

申请号：US11073185

申请日：2005-03-03

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

IPC分类号： H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forms a layer of strained-Si overlying the first and second SiGe layers; forms a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forms an p-well in the substrate and the overlying first layer of SiGe; forming forms a p-well in the substrate and the overlying second layer of SiGe; forms channel regions, in the strained-Si, and forms PMOS and NMOS transistor source and drain regions.

摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成覆盖衬底并且邻近第一SiGe层的第二层松弛SiGe，其厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于第一SiGe层和第二SiGe层之间的浅沟槽隔离区; 在衬底和SiGe的上覆第一层中形成p阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

公开(公告)号：US06699764B1

公开(公告)日：2004-03-02

申请号：US10238146

申请日：2002-09-09

申请人： Douglas J. Tweet ,  Jer-shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Jer-shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21336

CPC分类号： H01L21/263 ,  C30B1/023 ,  C30B1/04 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/1054 ,  H01L29/165 ,  Y10S438/933

摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

摘要翻译： 在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在Si1-XGeX层上外延生长硅帽; 通过Si1-XGeX层将氢离子注入Si1-XGeX / Si界面以下约3nm至100nm之间的深度; 将Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

公开(公告)号：US4411734A

公开(公告)日：1983-10-25

申请号：US448279

申请日：1982-12-09

申请人： Jer-shen Maa

发明人： Jer-shen Maa

IPC分类号： H01L21/3213 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

CPC分类号： H01L21/32137

摘要： A method of forming and anisotropically etching a structure on a substrate, said structure being comprised of a layer of doped polycrystalline silicon having thereover a layer of tantalum silicide. The method comprises providing a layer of polycrystalline silicon on the substrate, doping the silicon to render it conductive, preparing the surface of the silicon for deposition of tantalum silicide by treatment with a carbon tetrafluoride/oxygen plasma, depositing tantalum silicide thereon tantalum rich, anisotropically plasma etching the two-layered structure with an etchant mixture of carbon tetrachloride, oxygen and nitrogen, annealing the tantalum silicide layer and, if desired, covering the resultant structure with a protective layer of oxide. In a preferred embodiment, the silicon layer is deposited in the amorphorus state and annealed to the polycrystalline state.

摘要翻译： 一种形成和各向异性蚀刻衬底上的结构的方法，所述结构由在其上有一层硅化钽的掺杂多晶硅层组成。 该方法包括在衬底上提供多晶硅层，掺杂硅以使其导电，通过用四氟化碳/氧等离子体处理制备硅表面以沉积硅化钽，在其上沉积钽硅化物，各向异性 用四氯化碳，氧和氮的蚀刻剂混合物等离子体蚀刻两层结构，退火硅化钽层，如果需要，用氧化物保护层覆盖所得结构。 在优选实施例中，硅层以非晶态沉积，并退火至多晶态。

公开(公告)号：US06780700B2

公开(公告)日：2004-08-24

申请号：US10035503

申请日：2001-10-25

申请人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

发明人： Katsuji Iguchi ,  Sheng Teng Hsu ,  Yoshi Ono ,  Jer-shen Maa

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.

摘要翻译： 一种在硅衬底上形成MOS器件或CMOS器件的方法，包括制备衬底以包含其中具有器件有源区的导电区; 在有源区上形成栅电极; 在每个栅电极上沉积和形成栅电极侧壁绝缘体层; 注入第一类型的离子以在一个有效区域中形成源极区域和漏极区域，并且注入第二类型的离子，以在另一个有源区域中形成源极区域和漏极区域。

公开(公告)号：US06720258B2

公开(公告)日：2004-04-13

申请号：US10319313

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L29/456

摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

摘要翻译： 集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。 钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有 任何取向偏好，从而形成均匀的硅化镍层。 可以将镍硅化物退火以形成均匀的结晶二硅化镍。 因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

公开(公告)号：US06682995B2

公开(公告)日：2004-01-27

申请号：US10317742

申请日：2002-12-11

申请人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L213205

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

摘要翻译： 已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。 该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。 已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。 这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。 使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。 还提供了形成多层Ir导电结构和Ir铁电电极的方法。

公开(公告)号：US06583000B1

公开(公告)日：2003-06-24

申请号：US10072183

申请日：2002-02-07

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-shen Maa ,  Douglas James Tweet

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-shen Maa ,  Douglas James Tweet

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/76224 ,  H01L21/823878

摘要： A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.

摘要翻译： 形成CMOS器件的方法包括制备硅衬底，包括在衬底上形成多个器件区域; 在衬底上外延地形成应变SiGe层，其中SiGe层的锗含量在约20％和40％之间; 在SiGe层上外延地形成硅帽层; 沉积栅氧化层; 沉积第一多晶硅层; 将H +离子注入SiGe层以下的深度; 通过延伸到衬底中的浅沟槽隔离形成沟槽; 在约700℃至900℃的温度下退火结构约5分钟至60分钟; 沉积氧化物层和第二多晶硅层，从而填充沟槽; 将结构平面化到位于沟槽中的第二多晶硅层的部分的顶部的顶部; 并完成CMOS设备。

公开(公告)号：US06468901B1

公开(公告)日：2002-10-22

申请号：US09847873

申请日：2001-05-02

申请人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

发明人： Jer-shen Maa ,  Yoshi Ono ,  Fengyan Zhang

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.

摘要翻译： 一种集成电路器件及其制造方法，包括用铱中间层制造的硅衬底上的硅化镍。 在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积铱（Ir）界面层。 通过添加薄铱层，热稳定性大大提高。 即使在850℃退火之后，超浅结的低结漏电流和硅化物的薄片电阻也被示出。