公开(公告)号：US20090137178A1

公开(公告)日：2009-05-28

申请号：US12351983

申请日：2009-01-12

申请人： Masayuki SAKAKURA ,  Hiromichi GODO ,  Kaoru TSUCHIYA

发明人： Masayuki SAKAKURA ,  Hiromichi GODO ,  Kaoru TSUCHIYA

IPC分类号： H01J9/20

CPC分类号： H01L51/5246 ,  H01L23/564 ,  H01L27/124 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L33/44 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2251/5323 ,  H05B33/04 ,  H05B33/14 ,  Y10T428/24777

摘要： A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided. According to the present invention, a display device and a method of manufacturing the same comprising: a display portion formed by aligning a light-emitting element using an organic light-emitting material between a pair of substrate, wherein the display portion is formed on an insulating layer formed on any one of the substrates, the pair of substrates is bonded to each other with a sealing material formed over the insulating layer while surrounding a periphery of the display portion, at least one layer of the insulating layer is made of an organic resin material, the periphery has a first region and a second region, the insulating layer in the first region has an opening covered with a protective film, the sealing material is formed in contact with the opening and the protective film, an outer edge portion of the insulating layer in the second region is covered with the protective film or the sealing material.

摘要翻译： 提供了一种具有较高可靠性的具有阻挡水分和氧气结构，从而使显示装置的特性劣化的新型显示装置不会渗入密封区域及其制造方法。 根据本发明，一种显示装置及其制造方法，包括：显示部分，其通过使用有机发光材料在一对基板之间对准发光元件而形成，其中所述显示部分形成在 绝缘层形成在任何一个基板上，一对基板通过形成在绝缘层上的密封材料彼此接合，同时围绕显示部分的周围，至少一层绝缘层由有机物 树脂材料的周边具有第一区域和第二区域，第一区域中的绝缘层具有覆盖有保护膜的开口，密封材料形成为与开口和保护膜接触，外部边缘部分 第二区域中的绝缘层被保护膜或密封材料覆盖。

公开(公告)号：US20120187475A1

公开(公告)日：2012-07-26

申请号：US13354599

申请日：2012-01-20

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO

IPC分类号： H01L29/78

CPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7869

摘要： A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.

摘要翻译： 需要以几十毫秒的间隔刷新常规DRAM以保存数据，这导致大的功耗。 此外，其中的晶体管经常被打开和关闭; 因此，晶体管的劣化也是一个问题。 随着存储容量的增加和晶体管小型化的发展，这些问题变得越来越重要。 提供了一种晶体管，其包括宽间隙半导体，并且具有包括用于栅电极的沟槽和用于元件隔离的沟槽的沟槽结构。 即使当源电极和漏电极之间的距离减小时，通过适当地设置栅电极的沟槽的深度，可以抑制短沟道效应的发生。

公开(公告)号：US20120032236A1

公开(公告)日：2012-02-09

申请号：US13277489

申请日：2011-10-20

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromichi GODO ,  Yutaka OKAZAKI

IPC分类号： H01L27/092

CPC分类号： H01L27/1266 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/433 ,  H01L23/481 ,  H01L23/552 ,  H01L27/0688 ,  H01L27/1214 ,  H01L27/1229 ,  H01L29/7843 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/16152 ,  H01L2924/16195

摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.

摘要翻译： 目的是在具有SOI结构的半导体器件中实现高性能和低功耗。 此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。 半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。 通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和 可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

公开(公告)号：US20110180796A1

公开(公告)日：2011-07-28

申请号：US13008285

申请日：2011-01-18

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/24

CPC分类号： H01L29/7869

摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.

摘要翻译： 本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层， 其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

公开(公告)号：US20110133178A1

公开(公告)日：2011-06-09

申请号：US12957434

申请日：2010-12-01

申请人： Shunpei YAMAZAKI ,  Daisuke KAWAE ,  Hiromichi GODO

发明人： Shunpei YAMAZAKI ,  Daisuke KAWAE ,  Hiromichi GODO

IPC分类号： H01L27/092 ,  H01L29/12

CPC分类号： H01L29/45 ,  H01L27/1225 ,  H01L29/7869

摘要： One object is to provide a p-channel transistor including an oxide semiconductor. Another object is to provide a complementary metal oxide semiconductor (CMOS) structure of an n-channel transistor including an oxide semiconductor and a p-channel transistor including an oxide semiconductor. A p-channel transistor including an oxide semiconductor includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer, and a source and drain electrode layers in contact with the oxide semiconductor layer. When the electron affinity and the band gap of an oxide semiconductor used for the oxide semiconductor layer in the semiconductor device, respectively, are χ (eV) and Eg (eV), the work function (φm) of the conductor used for the source electrode layer and the drain electrode layer satisfies φm>χ+Eg/2 and the barrier for holes (φBp) represented by (χ+Eg−φm) is less than 0.25 eV.

摘要翻译： 一个目的是提供一种包括氧化物半导体的p沟道晶体管。 另一个目的是提供包括氧化物半导体的n沟道晶体管和包括氧化物半导体的p沟道晶体管的互补金属氧化物半导体（CMOS）结构。 包括氧化物半导体的p沟道晶体管包括与氧化物半导体层接触的栅极电极层，栅极绝缘层，氧化物半导体层以及源极和漏极电极层。 当半导体器件中用于氧化物半导体层的氧化物半导体的电子亲和力和带隙分别为χ（eV）和Eg（eV）时，用于该半导体器件的导体的功函数（＆phgr; m） 源电极层和漏电极层满足＆lt; m +χ+ Eg / 2，并且由（χ+ Eg-＆phgr; m）表示的空穴屏障（＆phgr; Bp）小于0.25eV。

公开(公告)号：US20100258802A1

公开(公告)日：2010-10-14

申请号：US12754393

申请日：2010-04-05

申请人： Hiromichi GODO ,  Takayuki INOUE

发明人： Hiromichi GODO ,  Takayuki INOUE

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： An object is to provide an n-channel transistor and a p-channel transistor having a preferred structure using an oxide semiconductor. A first source or drain electrode which is electrically connected to a first oxide semiconductor layer and is formed using a stacked-layer structure including a first conductive layer containing a first material and a second conductive layer containing a second material, and a second source or drain electrode which is electrically connected to a second oxide semiconductor layer and is formed using a stacked-layer structure including a third conductive layer containing the first material and a fourth conductive layer containing the second material are included. The first oxide semiconductor layer is in contact with the first conductive layer of the first source or drain electrode, and the second oxide semiconductor layer is in contact with the third and the fourth conductive layers of the second source or drain electrode.

摘要翻译： 目的是提供使用氧化物半导体的具有优选结构的n沟道晶体管和p沟道晶体管。 第一源极或漏极，其电连接到第一氧化物半导体层，并且使用包括包含第一材料的第一导电层和包含第二材料的第二导电层的堆叠层结构形成，以及第二源极或漏极 电连接到第二氧化物半导体层并且使用包括包含第一材料的第三导电层和包含第二材料的第四导电层的层叠结构形成的电极。 第一氧化物半导体层与第一源极或漏极的第一导电层接触，并且第二氧化物半导体层与第二源极或漏极的第三导电层和第四导电层接触。

公开(公告)号：US20100207118A1

公开(公告)日：2010-08-19

申请号：US12699974

申请日：2010-02-04

申请人： Junichiro SAKATA ,  Hiromichi GODO ,  Takashi SHIMAZU

发明人： Junichiro SAKATA ,  Hiromichi GODO ,  Takashi SHIMAZU

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L29/78669 ,  H01L29/78696

摘要： To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

摘要翻译： 为了抑制包括氧化物半导体层的晶体管或包括晶体管的半导体器件的电特性的劣化。 在其中使用氧化物半导体形成沟道层的晶体管中，提供与氧化物半导体层的表面接触的硅层。 此外，硅层设置成与至少形成沟道的氧化物半导体层的区域接触，并且提供与氧化物半导体层的区域接触的源电极层和漏电极层， 不提供硅层。

公开(公告)号：US20100148175A1

公开(公告)日：2010-06-17

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US20090278203A1

公开(公告)日：2009-11-12

申请号：US12504847

申请日：2009-07-17

申请人： Hiromichi GODO

发明人： Hiromichi GODO

IPC分类号： H01L27/12

CPC分类号： H01L29/66757 ,  H01L27/1255 ,  H01L29/78675

摘要： It is an object to reduce the effect of a characteristic of the edge portion of a channel forming region in a semiconductor film, on a transistor characteristic. An island-like semiconductor film is formed over a substrate, and a conductive film forming a gate electrode provided over the island-like semiconductor film with a gate insulating film interposed therebetween, is formed over the semiconductor film. In the semiconductor film, a channel forming region, a first impurity region forming a source or drain region, and a second impurity region are provided. The channel forming region is provided in a region which overlaps with the gate electrode crossing the island-like semiconductor film, the first impurity region is provided so as to be adjacent to the channel forming region, and the second impurity region is provided so as to be adjacent to the channel forming region and the first impurity region. The first impurity region and the second impurity region are provided so as to have different conductivity, and the second impurity region and the channel forming region are made to have different conductivity or to have different concentration of an impurity element contained in the second impurity region and the channel forming region in a case of having the same conductivity.

摘要翻译： 本发明的目的是减小半导体膜中的沟道形成区域的边缘部分的特性对晶体管特性的影响。 在衬底上形成岛状半导体膜，并且在半导体膜上形成形成设置在岛状半导体膜上的栅极的导电膜，其间插入有栅极绝缘膜。 在半导体膜中，设置沟道形成区域，形成源区或漏区的第一杂质区和第二杂质区。 通道形成区域设置在与栅极电极交叠的区域中，与岛状半导体膜交叉，第一杂质区域设置成与沟道形成区域相邻，并且第二杂质区域被设置为 与沟道形成区域和第一杂质区域相邻。 第一杂质区域和第二杂质区域被设置为具有不同的导电性，并且使第二杂质区域和沟道形成区域具有不同的导电性或者使第二杂质区域中包含的杂质元素的浓度不同，以及 在具有相同导电性的情况下的沟道形成区域。

公开(公告)号：US20090218568A1

公开(公告)日：2009-09-03

申请号：US12391398

申请日：2009-02-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。