公开(公告)号：US20250105184A1

公开(公告)日：2025-03-27

申请号：US18883834

申请日：2024-09-12

Applicant: MEDIATEK INC.

Inventor： Kai-Lun KUO ,  Kun-Ting TSAI ,  Che-Hung KUO

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: An electronic device is provided. The electronic device includes a semiconductor die. The semiconductor die has a first region of a first functional cell close to the peripheral edge of the semiconductor die. The semiconductor die includes a semiconductor substrate, a first signal bump, and a first power bump. The first signal bump and the first power bump are disposed on opposite surfaces of the semiconductor substrate and electrically connected to the first functional cell. The first signal bump and the first power bump both overlap the first region.

公开(公告)号：US20190131233A1

公开(公告)日：2019-05-02

申请号：US16232129

申请日：2018-12-26

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

公开(公告)号：US20240079308A1

公开(公告)日：2024-03-07

申请号：US18365259

申请日：2023-08-04

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L25/105 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/48 ,  H01L2224/08235 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14361

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor die, a second semiconductor die and third semiconductor die. The first semiconductor die and the second semiconductor die are arranged side-by-side. The first semiconductor die includes a first interface and a second interface. The first interface is arranged on a first edge of the first semiconductor die. The second interface is arranged on a second edge of the first semiconductor die that is close to the second semiconductor die and connected to the first edge. The third semiconductor die is stacked on the first semiconductor die and the second semiconductor die, wherein the third semiconductor die is electrically connected to the first semiconductor die by the first interface, and wherein the first semiconductor die is electrically connected to the second semiconductor die by the second interface.

公开(公告)号：US20220367430A1

公开(公告)日：2022-11-17

申请号：US17739295

申请日：2022-05-09

Applicant: MEDIATEK INC.

Inventor： Yi-Jyun LEE ,  Duen-Yi HO ,  Hsing-Chih LIU ,  Che-Hung KUO

IPC: H01L25/16 ,  H01L49/02 ,  H01L23/498

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

公开(公告)号：US20170338175A1

公开(公告)日：2017-11-23

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Che-Hung KUO ,  Che-Ya CHOU ,  Wei-Che HUANG

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1421 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US20250105237A1

公开(公告)日：2025-03-27

申请号：US18893113

申请日：2024-09-23

Applicant: MEDIATEK INC.

Inventor： Chung-Min YANG ,  Che-Hung KUO

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L25/065 ,  H05K1/18 ,  H10B80/00

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first and a second semiconductor dies. The first semiconductor die has a first surface and a second surface opposite the first surface. The first semiconductor die includes a first interface and a second interface. The second interface is arranged beside the first interface. The second interface is farther from the corresponding first edge of the first semiconductor die than the first interface. The second semiconductor die is stacked on the first semiconductor die. The semiconductor package assembly further includes a first conductive bump and a second conductive bump. The first conductive bump is disposed on the first surface of the first semiconductor die. The second conductive bump is disposed on the second surface of the first semiconductor die. The second semiconductor die is electrically coupled to the first semiconductor die by the second interface.

公开(公告)号：US20240332266A1

公开(公告)日：2024-10-03

申请号：US18405195

申请日：2024-01-05

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Ta-Jen YU ,  Chi-Hung HUANG

IPC: H01L25/10 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom package and a top package. The top package is mounted on the bottom package. At least one portion of the top package protrudes from a sidewall of the bottom package. The semiconductor device further includes a passive device mounted on a protruding region of the portion of the top package.

公开(公告)号：US20240063078A1

公开(公告)日：2024-02-22

申请号：US18497043

申请日：2023-10-30

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Chun-Yin LIN

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/367 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/162 ,  H01L24/48 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/16157 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48225 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/19011 ,  H01L2924/19041

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a thermal spreader, a molding material, and a second redistribution layer. The first semiconductor die and the second semiconductor die are disposed side-by-side over the first redistribution layer. The thermal spreader vertically overlaps with the first semiconductor die and/or the second semiconductor die. The molding material surrounds the thermal spreader, the first semiconductor die and the second semiconductor die. The second redistribution layer is disposed over the molding material.

公开(公告)号：US20240096861A1

公开(公告)日：2024-03-21

申请号：US18454220

申请日：2023-08-23

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Hsiao-Yun CHEN ,  Wen-Pin CHU ,  Chun-Hsiang HUANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5385 ,  H01L28/90 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

公开(公告)号：US20230317580A1

公开(公告)日：2023-10-05

申请号：US18329721

申请日：2023-06-06

Applicant: MEDIATEK INC.

Inventor： Hsing-Chih LIU ,  Zheng ZENG ,  Che-Hung KUO

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/5389 ,  H01L23/5385 ,  H01L25/105 ,  H01L23/481 ,  H01L25/0657 ,  H01L23/3128

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.