公开(公告)号：US20050280100A1

公开(公告)日：2005-12-22

申请号：US10870102

申请日：2004-06-17

申请人： Michael Artaki ,  Isik Kizilyalli ,  Zhijian Xie

发明人： Michael Artaki ,  Isik Kizilyalli ,  Zhijian Xie

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/1045 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： Significant improvement in gain is achievable in a laterally diffused MOS device without substantial change in threshold voltage. Such improvement in a device having a channel with lateral dopant gradient of at least a factor of 10 per micrometer of channel is attained using a P-type gate. For example, a gm of 0.02 S/mm (at VDS=28 V) and a drain breakdown of more than 70V with gate oxide of 350 Å is possible with a threshold voltage of 3.5 volts.

摘要翻译： 在横向扩散的MOS器件中可以实现增益的显着改善，而阈值电压没有实质的变化。 使用P型栅极获得具有横向掺杂剂梯度通道至少为每微米通道10倍的通道的器件的这种改进。 例如，在阈值电压为3.5伏的情况下，可以使用0.02S / mm（VDS = 28V）和大于70V的栅极氧化物的漏极击穿。

公开(公告)号：US20050156234A1

公开(公告)日：2005-07-21

申请号：US10977732

申请日：2004-10-29

申请人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L29/40 ,  H01L29/41 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/402 ,  H01L29/41 ,  H01L29/7835

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.

摘要翻译： 形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域 相对于彼此间隔开。 在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。 绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。 栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。 屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

公开(公告)号：US20080003703A1

公开(公告)日：2008-01-03

申请号：US11853417

申请日：2007-09-11

申请人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L21/66

CPC分类号： H01L29/402 ,  H01L29/41 ,  H01L29/7835

摘要： In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.

摘要翻译： 在包括形成在靠近半导体层的上表面的第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域的金属氧化物半导体器件中，形成在靠近上部的半导体层中的漂移区域 半导体层的表面，并且至少部分地在第一和第二源极/漏极区之间，形成在半导体层的上表面的至少一部分上的绝缘层和形成在绝缘层上的栅极，并且至少部分地在第一和/ 第一和第二源极/漏极区域，用于控制器件中热载流子注入劣化量的方法包括以下步骤：在绝缘层上形成屏蔽结构，该屏蔽结构位于漂移区域的至少一部分上方并且基本上在栅极 和第二源极/漏极区域; 以及调整所述屏蔽结构在所述漂移区域的上表面上的覆盖范围，以便在保持所述器件中的击穿电压大于或等于规定值的同时使热载流子注入劣化的量最小化。

公开(公告)号：US20070001243A1

公开(公告)日：2007-01-04

申请号：US11438493

申请日：2006-05-22

申请人： Isik Kizilyalli ,  Joseph Radosevich ,  Pradip Roy

发明人： Isik Kizilyalli ,  Joseph Radosevich ,  Pradip Roy

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/76814 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66659

摘要： A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated. A circuit comprises a semiconductor material having a surface region for formation of devices, a field effect transistor gate structure formed on the surface region, the gate structure including a conductive layer and an amorphous insulative layer having a dielectric constant greater than five relative to free space. The insulative layer is formed between the conductive layer and the surface region. A source region is formed along the surface region and a drain region is also formed along the surface region. The gate structure, source region and drain region are configured to form an operable field effect transistor.

摘要翻译： 一种用于半导体电子产品和电路结构的制造方法。 半导体材料具有表面区域，并且掺杂剂被提供到表面区域的一部分。 用足够的能量照射设置有掺杂剂的表面区域的部分，以引起掺杂剂从表面区域的部分扩散到半导体材料的另一区域。 一种制造具有半导体材料的电子产品的方法，所述半导体材料具有沿表面的两个间隔开的区域，用于接收掺杂剂包括：沿两个间隔开的表面的表面和表面的第三区域上形成场效应晶体管栅极结构 地区。 将掺杂剂提供给间隔开的区域，其被加热到高于在加热间隔开的区域时导致第三区域的峰值温度至少50摄氏度的温度。 电路包括具有用于形成器件的表面区域的半导体材料，形成在表面区域上的场效应晶体管栅极结构，所述栅极结构包括导电层和相对于自由空间具有大于5的介电常数的非晶绝缘层 。 绝缘层形成在导电层和表面区域之间。 沿着表面区域形成源极区域，并且还沿着表面区域形成漏极区域。 栅极结构，源极区和漏极区被配置成形成可操作的场效应晶体管。

公开(公告)号：US07494888B2

公开(公告)日：2009-02-24

申请号：US10875029

申请日：2004-06-23

申请人： Peter L. Gammel ,  Bailey R. Jones ,  Isik Kizilyalli ,  Hugo F. Safar

发明人： Peter L. Gammel ,  Bailey R. Jones ,  Isik Kizilyalli ,  Hugo F. Safar

IPC分类号： H01L21/331

CPC分类号： H01L29/16 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/322 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.

摘要翻译： 本发明提供一种可并入集成电路的半导体器件的制造方法。 该方法包括：在基础衬底上形成同位素富集的硅的第一掺杂层，在第一掺杂层上形成同位素富集的半导体材料硅的第二层，以及在第二层上构建有源器件。 该器件包括同位素富集的半导体材料的第一掺杂层和位于第一掺杂层上方的同位素富集的半导体材料的第二层以及位于第二层上的有源器件。

公开(公告)号：US20060113625A1

公开(公告)日：2006-06-01

申请号：US10999704

申请日：2004-11-30

申请人： Jeff Bude ,  Isik Kizilyalli ,  Kent Smith

发明人： Jeff Bude ,  Isik Kizilyalli ,  Kent Smith

IPC分类号： H01L23/58

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/402

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are spaced apart relative to one another. A drift region of the second conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the source and drain regions, the drift region having an impurity doping concentration greater than about 2.0e12 atoms/cm2. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer. The device further includes a gate formed on the insulating layer at least partially between the source and drain regions, and a buried layer of the first conductivity type formed in the semiconductor layer in close relative proximity to and beneath at least a portion of the drift region. A substantially vertical distance between the buried layer and the drift region, and/or one or more physical dimensions of the buried layer are configured so as to optimize a power density of the device relative to at least one of an on-resistance and a maximum drain current of the device.

摘要翻译： 形成MOS器件，其包括第一导电类型的半导体层，以及形成在半导体层中的靠近半导体层的上表面的第二导电类型的源区和漏区。 源区和漏区彼此间隔开。 第二导电类型的漂移区形成在靠近半导体层的上表面的半导体层中并且至少部分地在源极和漏极区之间，漂移区具有大于约2.0e12原子/ cm 2的杂质掺杂浓度， SUP> 2 。 绝缘层形成在半导体层的上表面的至少一部分上。 所述器件还包括至少部分地在所述源极和漏极区域之间形成在所述绝缘层上的栅极，以及形成在所述半导体层中的所述第一导电类型的掩埋层彼此靠近并且位于所述漂移区域的至少一部分 。 掩埋层和漂移区之间的基本上垂直的距离和/或掩埋层的一个或多个物理尺寸被配置为优化器件相对于导通电阻和最大值中的至少一个的功率密度 漏极电流。

公开(公告)号：US20140048903A1

公开(公告)日：2014-02-20

申请号：US13586330

申请日：2012-08-15

申请人： Andrew Edwards ,  Hui Nie ,  Isik Kizilyalli ,  Dave Bour

发明人： Andrew Edwards ,  Hui Nie ,  Isik Kizilyalli ,  Dave Bour

IPC分类号： H01L29/872 ,  H01L21/20

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure.

摘要翻译： 一种用于制造氮化镓（GaN）材料中的边缘端接结构的方法包括提供具有第一表面和第二表面的n型GaN衬底，形成耦合到n型GaN的第一表面的n型GaN外延层 并且通过使用第一离子注入在n型GaN外延层中形成一个或多个p型区域。 一个或多个p型区域中的至少一个包括边缘终端结构。

公开(公告)号：US08558242B2

公开(公告)日：2013-10-15

申请号：US13315705

申请日：2011-12-09

申请人： Richard J. Brown ,  Hui Nie ,  Andrew Edwards ,  Isik Kizilyalli ,  David Bour ,  Thomas Prunty ,  Linda Romano ,  Madhan Raj

发明人： Richard J. Brown ,  Hui Nie ,  Andrew Edwards ,  Isik Kizilyalli ,  David Bour ,  Thomas Prunty ,  Linda Romano ,  Madhan Raj

IPC分类号： H01L29/20

CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7828

摘要： A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.

摘要翻译： 半导体结构包括具有顶表面和相对底表面的III族氮化物衬底和与III族氮化物衬底的顶表面耦合的第一导电类型的第一III族氮化物层。 半导体结构还包括沿着垂直方向耦合到第一III族氮化物层的第二导电类型的第二III族氮化物层，以及沿着沿着垂直方向耦合到第二III族氮化物层的第三导电类型的第三III族氮化物层 垂直方向 半导体结构还包括延伸穿过第三III族氮化物层的一部分到第一III族氮化物层的第一沟槽，延伸穿过第三III族氮化物层的另一部分到第二III族氮化物层的第二沟槽，以及 耦合到第二和第三III族氮化物层的第一金属层。

公开(公告)号：US20130146885A1

公开(公告)日：2013-06-13

申请号：US13315705

申请日：2011-12-09

申请人： Richard J. Brown ,  Hui Nei ,  Andrew Edwards ,  Isik Kizilyalli ,  David Bour ,  Thomas Prunty ,  Linda Romano ,  Madhan Raj

发明人： Richard J. Brown ,  Hui Nei ,  Andrew Edwards ,  Isik Kizilyalli ,  David Bour ,  Thomas Prunty ,  Linda Romano ,  Madhan Raj

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7828

摘要： A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.

摘要翻译： 半导体结构包括具有顶表面和相对底表面的III族氮化物衬底和与III族氮化物衬底的顶表面耦合的第一导电类型的第一III族氮化物层。 半导体结构还包括沿着垂直方向耦合到第一III族氮化物层的第二导电类型的第二III族氮化物层，以及沿着沿着垂直方向耦合到第二III族氮化物层的第三导电类型的第三III族氮化物层 垂直方向 半导体结构还包括延伸穿过第三III族氮化物层的一部分到第一III族氮化物层的第一沟槽，延伸穿过第三III族氮化物层的另一部分到第二III族氮化物层的第二沟槽，以及 耦合到第二和第三III族氮化物层的第一金属层。

公开(公告)号：US20100140665A1

公开(公告)日：2010-06-10

申请号：US11839030

申请日：2007-08-15

申请人： Sameer Singbal ,  Andrew Edwards ,  Chul H. Park ,  Quinn Martin ,  Isik Kizilyalli

发明人： Sameer Singbal ,  Andrew Edwards ,  Chul H. Park ,  Quinn Martin ,  Isik Kizilyalli

IPC分类号： H01L27/08 ,  H01L21/60 ,  H01L29/20 ,  H01L21/77 ,  H01L23/52

CPC分类号： H01L27/0605 ,  H01L23/4824 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/78681 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/10158 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

摘要： Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and lifetime.

摘要翻译： 描述了与装置相关的氮化镓材料装置和方法。 这些器件可以设计成提供增强的热传导和降低的热阻。 通过和移出氮化镓器件的增加的热传导增强了器件的可操作性，包括提供优异的RF操作，可靠性和寿命。