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23 条记录 (耗时 0.035 秒)

    Process of forming copper structures
    2.
    发明授权
    Process of forming copper structures 失效
    形成铜结构的工艺

    公开(公告)号：US06812143B2

    公开(公告)日：2004-11-02

    申请号：US10279057

    申请日：2002-10-24

    申请人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    发明人： Michael Lane ,  Fenton Read McFeely ,  Conal Murray ,  Robert Rosenberg

    IPC分类号： H01L2144

    CPC分类号： H01L21/32051 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

    摘要翻译： 本发明的阻挡材料提供铜的电沉积。 阻挡层包括介电界面表面区域和具有至少50原子百分比的铜界面金属的铜界面表面区域。 特别地，本发明的阻挡层提供在直接电沉积工艺中将铜或铜合金直接电沉积在阻挡层的铜界面区域上。 该方法包括提供设置在底层上的电介质层，使阻挡层与电介质层接触，并将导电层沉积在阻挡层上。

    Method for depositing metal films onto substrate surfaces utilizing a chamfered ring support
    5.
    发明授权
    Method for depositing metal films onto substrate surfaces utilizing a chamfered ring support 失效
    使用倒角环支撑体将金属膜沉积到基板表面上的方法

    公开(公告)号：US06660330B2

    公开(公告)日：2003-12-09

    申请号：US09829648

    申请日：2001-04-10

    申请人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

    发明人： Peter S. Locke ,  Sandra Guy Malhotra ,  Fenton Read McFeely ,  Andrew Herbert Simon ,  John Jacob Yurkas

    IPC分类号： C23C1606

    CPC分类号： C23C16/466 ,  C23C16/481 ,  H01L21/28556 ,  H01L21/67109

    摘要： The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.

    摘要翻译： 本发明涉及一种在基板表面上的金属膜的低压化学气相沉积（CVD）期间确保变形耐受基板的均匀可重复加热的方法和装置。 在本发明中通过将衬底定位在位于CVD反应器室中的加热元件上方的倒角环的斜面上来实现衬底的均匀和可再现的加热。 加热元件，倒角环和衬底底面之间的空间限定了衬底和加热元件之间的空腔，确保衬底被辐射装置加热而不是直接接触。

    Growth of epitaxial semiconductor films in presence of reactive metal
    6.
    发明授权
    Growth of epitaxial semiconductor films in presence of reactive metal 失效
    外延半导体膜在活性金属存在下的生长

    公开(公告)号：US06211042B1

    公开(公告)日：2001-04-03

    申请号：US09170621

    申请日：1998-10-13

    申请人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

    发明人： Fenton Read McFeely ,  Ismail Cevdet Noyan ,  John Jacob Yurkas

    IPC分类号： H01L2120

    CPC分类号： H01L21/28518 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

    摘要： A method is disclosed for forming an epitaxial layer of a semiconductor material over a metal structure disposed upon a surface of a semiconductor substrate, the metal being characterized by a negative Gibbs free energy for the formation of a compound of the metal and the semiconductor material. The method comprises the steps of: a) placing the substrate in a reactor vessel having a base pressure in the ultra high vacuum range, b) bringing the substrate to an elevated temperature, and c) flowing, over said substrate, a halogen-free precursor gas of molecules comprising the semiconductor material. Typically, the metal structure characterized by feature dimensions of less than 2.0 microns. Preferably, the metal is tungsten, the semiconductor material is silicon and the gas comprises a silane of the form SinH(2n+2), where n is a positive integer.

    摘要翻译： 公开了一种用于在半导体衬底的表面上形成半导体材料外延层的方法，该金属结构设置在金属结构的表面上，该金属的特征在于用于形成金属和半导体材料的化合物的负的吉布斯自由能。 该方法包括以下步骤：a）将基板放置在基本压力在超高真空范围内的反应器容器中，b）使基板升高温度，和c）在所述基板上流过无卤素 包含半导体材料的分子的前体气体。 通常，特征尺寸小于2.0微米的金属结构。 优选地，金属是钨，半导体材料是硅，气体包括形式为SinH（2n + 2）的硅烷，其中n是正整数。

    Method and Structure to Improve the Conductivity of Narrow Copper Filled Vias
    7.
    发明申请
    Method and Structure to Improve the Conductivity of Narrow Copper Filled Vias 有权
    提高窄铜填充通孔电导率的方法和结构

    公开(公告)号：US20120012372A1

    公开(公告)日：2012-01-19

    申请号：US12838597

    申请日：2010-07-19

    申请人： Fenton Read McFeely ,  Chih-Chao Yang

    发明人： Fenton Read McFeely ,  Chih-Chao Yang

    IPC分类号： H05K1/09 ,  H01B13/00

    CPC分类号： H05K1/09 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

    摘要： Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

    摘要翻译： 提供了提高铜（Cu）填充通孔电导率的技术。 一方面，提供一种制造填充铜的通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 在Ru层上沉积薄的种子Cu层。 进行第一退火以增加种子Cu层的晶粒尺寸。 通孔填充有额外的铜。 进行第二次退火以增加附加Cu的晶粒尺寸。

    Multi-Step Method to Selectively Deposit Ruthenium Layers of Arbitrary Thickness on Copper
    10.
    发明申请
    Multi-Step Method to Selectively Deposit Ruthenium Layers of Arbitrary Thickness on Copper 审中-公开
    选择性沉积铜上任意厚度的钌层的多步法

    公开(公告)号：US20110045171A1

    公开(公告)日：2011-02-24

    申请号：US12544110

    申请日：2009-08-19

    申请人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jcobs Yurkas

    发明人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jcobs Yurkas

    IPC分类号： B05D5/12

    CPC分类号： C23C16/16 ,  C23C16/04 ,  C23C16/56 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76849 ,  H01L21/7685

    摘要： Techniques for forming a ruthenium (Ru) capping layer on a copper (Cu) wire are provided. In one aspect, a method of forming a Ru capping layer on at least one exposed surface of a Cu wire embedded in a dielectric structure includes the following steps. A first Ru layer is selectively deposited onto the Cu wire and the dielectric structure by chemical vapor deposition (CVD) for a period of time during which selective nucleation of the Ru occurs on the surface of the Cu wire. Any nucleated Ru present on the dielectric structure is oxidized. The oxidized Ru and an aqueous acid are contacted to remove the oxidized Ru from the dielectric structure based on a selectivity of the aqueous acid in dissolving the oxidized Ru. A second Ru layer is selectively deposited onto the first Ru layer by CVD to produce a thicker Ru layer. The steps of oxidizing and contacting the oxidized Ru and an aqueous acid are repeated until a Ru layer having a thickness that is suitable for use as a Ru capping layer on at least one exposed surface of the Cu wire embedded in the dielectric structure is achieved.

    摘要翻译： 提供了在铜（Cu）线上形成钌（Ru）覆盖层的技术。 一方面，在嵌入电介质结构的Cu线的至少一个露出表面上形成Ru覆盖层的方法包括以下步骤。 通过化学气相沉积（CVD）在Cu线和电介质结构上选择性地将第一Ru层沉积在Cu线的表面上发生Ru的选择性成核的一段时间。 存在于电介质结构上的任何成核Ru被氧化。 接触氧化的Ru和酸水以从介电结构中除去氧化的Ru，这是基于酸水溶解氧化Ru的选择性。 通过CVD将第二Ru层选择性地沉积到第一Ru层上以产生更厚的Ru层。 重复氧化和接触氧化的Ru和酸性水的步骤，直到达到在埋入电介质结构的Cu线的至少一个暴露表面上适合用作Ru覆盖层的厚度的Ru层。