公开(公告)号：US4002875A

公开(公告)日：1977-01-11

申请号：US621620

申请日：1975-10-10

申请人： Mitsuyuki Kiuchi ,  Shigeru Kusunoki ,  Hiroshi Fujieda ,  Keizo Amagami ,  Tadao Toyooka

发明人： Mitsuyuki Kiuchi ,  Shigeru Kusunoki ,  Hiroshi Fujieda ,  Keizo Amagami ,  Tadao Toyooka

IPC分类号： F24C7/02 ,  H02M7/523 ,  H03B9/10 ,  H05B6/06 ,  H05B6/12 ,  H05B6/68 ,  H05B11/00 ,  H05B9/06

CPC分类号： H05B6/6488 ,  F24C7/02 ,  H02M7/523 ,  H03B9/10 ,  H05B6/681

摘要： A high frequency heating apparatus in which a combination of a microwave oven for heating food through dielectric heating and a cooking device for heating metallic vessel through electrical induction is incorporated to effect efficient cooking and simultaneous formation of brown scorching on the surface of food. In the heating apparatus, power required for the magnetron of the microwave oven and also for the heating coil of the cooking device is supplied through one inverter unit, by which arrangement, an efficient cooking apparatus of compact size is presented.

摘要翻译： 一种高频加热装置，其中结合了通过介电加热加热食物的微波炉和通过电感应加热金属容器的烹饪装置的组合，以实现食品表面上的高效烹饪和同时形成棕色焦烧。 在加热装置中，通过一个逆变器单元供给微波炉的磁控管和烹调装置的加热线圈所需的功率，通过该逆变器单元提供了紧凑尺寸的有效的烹饪设备。

公开(公告)号：US09041097B2

公开(公告)日：2015-05-26

申请号：US13849344

申请日：2013-03-22

申请人： Shigeru Kusunoki

发明人： Shigeru Kusunoki

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/739 ,  H01L29/49

CPC分类号： H01L29/66666 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/4232 ,  H01L29/4916 ,  H01L29/7397

摘要： A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer.

摘要翻译： 半导体器件包括形成在衬底上的沟道层，与沟道层接触形成的绝缘层，形成在绝缘层与沟道层相反的一侧的杂质掺杂的第一半导体层，杂质掺杂的第二半导体 在第一半导体层的与绝缘层相反的一侧形成的层，以及形成在第二半导体层与第一半导体层相反的一侧上的栅电极。 第一半导体层的杂质浓度除以第一半导体层的相对介电常数的商大于第二半导体层的杂质浓度除以第二半导体层的相对介电常数的商。

公开(公告)号：US08853737B2

公开(公告)日：2014-10-07

申请号：US13493745

申请日：2012-06-11

申请人： Shigeru Kusunoki

发明人： Shigeru Kusunoki

IPC分类号： H01L29/739 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L49/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H03K17/08

CPC分类号： H01L29/7396 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0921 ,  H01L28/20 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7817 ,  H01L29/7824 ,  H01L2924/0002 ,  H03K17/08 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.

摘要翻译： 半导体器件包括半导体衬底，其包括半导体层，形成在半导体衬底中的功率器件，形成在半导体衬底中并围绕功率器件的多个同心保护环;以及电压施加装置，用于分别向 多个同心保护环，最外面的同心保护环具有施加到其上的最高电压。

公开(公告)号：US08847290B2

公开(公告)日：2014-09-30

申请号：US13729584

申请日：2012-12-28

申请人： Shigeru Kusunoki ,  Shinichi Ishizawa

发明人： Shigeru Kusunoki ,  Shinichi Ishizawa

IPC分类号： H01L29/66 ,  H01L27/06

CPC分类号： H01L27/0629

摘要： A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

摘要翻译： 半导体器件包括：整流元件; 电连接到整流元件的电极垫; 以及布置在整流元件和电极焊盘之间的电阻和耗尽晶体管，并且彼此电连接。 半导体器件具有其中整流元件，电阻，耗尽晶体管和电极焊盘串联连接的结构。 半导体器件被配置为基于跨越电阻的电位差产生耗尽型晶体管的栅极电位，并且基于栅极电位在耗尽型晶体管的沟道中产生耗尽层。 结果，可以获得在低电压下具有相当大的电流并且在高电压下具有小的电流的半导体器件。

公开(公告)号：US07504707B2

公开(公告)日：2009-03-17

申请号：US10515346

申请日：2003-06-05

申请人： Norifumi Tokuda ,  Shigeru Kusunoki

发明人： Norifumi Tokuda ,  Shigeru Kusunoki

IPC分类号： H01L23/58

CPC分类号： H01L29/0696 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/7397 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.

公开(公告)号：US20090068815A1

公开(公告)日：2009-03-12

申请号：US12271544

申请日：2008-11-14

申请人： Norifumi Tokuda ,  Shigeru Kusunoki

发明人： Norifumi Tokuda ,  Shigeru Kusunoki

IPC分类号： H01L21/762

CPC分类号： H01L29/0696 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/7397 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in which a main current flows in a direction of the thickness of a semiconductor substrate, to attain desirable electric characteristics. P type semiconductor regions and N type semiconductor regions are alternately provided with an interval therebetween, both regions in a surface of a second main surface of a semiconductor substrate. Between the P type semiconductor regions and the N type semiconductor regions, trenches formed in the surface of the semiconductor substrate are filled with insulators, thereby forming trench isolation structures. Moreover, a second main electrode is formed in contact with both the P type semiconductor regions and the N type semiconductor regions.

摘要翻译： 主电流沿半导体衬底的厚度方向流动的半导体器件，以获得所需的电特性。 P型半导体区域和N型半导体区域在半导体衬底的第二主表面的表面中的两个区域之间交替设置有间隔。 在P型半导体区域和N型半导体区域之间，形成在半导体衬底的表面中的沟槽用绝缘体填充，从而形成沟槽隔离结构。 此外，第二主电极形成为与P型半导体区域和N型半导体区域接触。

公开(公告)号：US07250345B2

公开(公告)日：2007-07-31

申请号：US10976855

申请日：2004-11-01

申请人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

发明人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 μm and no greater than 250 μm and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

摘要翻译： 本发明的半导体器件具有电源装置，该功率器件具有：具有彼此相对的第一主表面和第二主表面的半导体衬底，以及在第一主表面侧的绝缘栅极结构，其中主电流 在第一主表面和第二主表面之间流动，即具有绝缘栅型MOS晶体管结构，其中半导体衬底的厚度（t 1> 1）不小于50 在第一主表面上实施了不超过250个妈妈的低导通电压和高耐破坏能力。 因此，可以实现低导通电压，耐击穿能力的保持和高压侧的开关损耗的降低。

公开(公告)号：US20050280029A1

公开(公告)日：2005-12-22

申请号：US11204048

申请日：2005-08-16

申请人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

发明人： Katsumi Nakamura ,  Shigeru Kusunoki ,  Hideki Nakamura

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/739 ,  H01L31/0328

CPC分类号： H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/7395 ,  H01L29/7397

摘要： A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n− silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n− silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n− silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n− silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n− silicon substrate (1).

摘要翻译： 本发明的半导体器件具有绝缘栅型场效应晶体管部分，其具有n型发射极区域（3）和n +硅衬底（1），它们彼此相对夹入 p型体区域（2）以及与栅极绝缘膜（4a）夹持的p型体区域（2）相对的栅电极（5a），还具有稳定板（5） b）。 该稳定板（5b）由导体或半导体制成，与夹在板上的绝缘膜（4,4b）夹在一起的n +硅衬底（1）相对，并形成在一起 与硅衬底（1），电容器。 形成在稳定板（5b）和硅衬底（1）之间的稳定板电容器的电容大于在栅电极（5a）和n < 硅衬底（1）。

公开(公告)号：US5341022A

公开(公告)日：1994-08-23

申请号：US31988

申请日：1993-03-16

申请人： Takashi Kuroi ,  Shigeru Kusunoki

发明人： Takashi Kuroi ,  Shigeru Kusunoki

IPC分类号： H01L21/265 ,  H01L21/322 ,  H01L21/331 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/32

CPC分类号： H01L29/66272 ,  H01L21/3221 ,  H01L29/0821 ,  Y10S148/01 ,  Y10S148/086 ,  Y10S257/928

摘要： A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.

摘要翻译： 在短时间内以低成本制造具有减小的漏电流的半导体器件，具有优异的可控性。 在半导体衬底上形成埋设层（20），该掩埋层（20）包括高离子浓度的主要埋置层（21），其含有从上下方向上的低离子浓度的二次掩埋层（3a，3b）夹入的二次缺陷（22） （1）。 二次缺陷（22）具有稳定的吸气效应，可减少晶体管（200）形成过程中产生的缺陷和重金属污染。 此外，二次埋层（3a，3b）防止耗尽层达到二次缺陷（22）。 半导体器件可以在短时间内形成，因为不使用外延生长。

公开(公告)号：US5336904A

公开(公告)日：1994-08-09

申请号：US864897

申请日：1992-04-02

申请人： Shigeru Kusunoki

发明人： Shigeru Kusunoki

IPC分类号： H01L29/68 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L29/10 ,  H01L29/772 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L27/12

CPC分类号： B82Y10/00 ,  H01L21/2022 ,  H01L29/1054 ,  H01L29/66621 ,  H01L29/772 ,  H01L29/78

摘要： A field effect transistor according to the present invention uses a silicon monocrystalline substrate. At least two independent thin amorphous silicon layers are formed in a position for preventing movement of majority carriers in a channel region in the surface of the silicon substrate. Each amorphous silicon layer is between monocrystalline silicon layers. A gate electrode is formed on the surface of the channel region through a gate insulating layer. Thin potential barriers and a potential well are formed in the channel region by at least two amorphous silicon layers. Sharp potential barriers are formed by forming thin amorphous silicon layers, and a field effect transistor utilizing the resonant-tunneling effect with high tunneling efficiency is implemented.

摘要翻译： 根据本发明的场效应晶体管使用硅单晶衬底。 至少两个独立的薄非晶硅层形成在用于防止硅衬底的表面中的沟道区中的多数载流子移动的位置。 每个非晶硅层在单晶硅层之间。 栅电极通过栅极绝缘层形成在沟道区的表面上。 通过至少两个非晶硅层在沟道区中形成薄势垒和势阱。 通过形成薄的非晶硅层形成尖锐的势垒，并且实现了利用具有高隧道效率的谐振隧穿效应的场效应晶体管。